SU1619313A1 - Device for input checking of articles - Google Patents

Abstract

The invention relates to automation v can be applied at the input control of products in production. The purpose of the invention is to increase the reliability and performance of the device by enabling the use of a co-trol sequential plan. The device contains a data input unit 1, a storage unit 2, a block 3, a calculator 4, a block 5 for inputting parameters, a block 6 for decision making and a block 7 for mapping. 2 hp ff, 9 silt ,, 1 tab.

Description

The invention relates to automation and can be used in incoming inspection of products in production.

The aim of the invention is to increase the reliability and performance of the device by allowing the use of a consistent control plan.

FIG. 1 shows a block diagram of the device, FIG. 2 - data entry unit; in fig. 3 - drive; in fig. 4 shows the control unit J in FIG. 5 - calculator $ in FIG. 6 - unit settings settings; in fig. 7 — decision unit; in fig. 8 — display unit; in fig. 9 is a temporary diagram of the operation of the device.

The device for input control of products includes a block of data input 1, a drive 2, a control block 3, a calculator 4 of the control plan, a parameter setting setting unit 5, a decision block 6 and a display block 7. The inputs and outputs of the unit and the device bus are indicated by the positions 8-52.

Data input unit 1 contains the first to the third pushbutton switches 53-55, the first 56 and the second 57 trigger, the first to the third elements 2 OR 58-60, the first 61 and the second 62 elements 2I and the element NOT 63 ..

The data entry unit 1 is designed to enter the results of control operations of the Goden type, Scrap into the storage unit 2, in the control unit 3 when operating the manual operation of the switches 53 and 54 and when operating from the automatic control equipment from inputs 8 and 9. Using the switch ( /: with

about with

UO

s

55, the installation of the initial (zero) state of accumulator 2, control block 3 and decision block 6 is carried out.

The drive 2 (FIG. 3) contains the first through the fourth binary-decimal counters 64 -64 and 65 -65, groups of amplifiers 66 -66 and 67 -67. Each amplifier is a four-AND-NOT element with an open collector.

The drive 2 is designed to count the number of good products i from input 52, the number of defective products z from input 11 and output to the tires (second 22 and fourth 50 outputs) binary-ten coded numbers of these data in accordance with the signals on the input tires (third 25 and fourth 49 entrances).

The control unit 3 (FIG. 4) consists of the RS-flip-flop 68h, the first element 2I 69, the binary counter 70, the permanent memory nodes 71, the elements 2I-2I-OR 72 and 73 of the delay element 74, the converter 75 codes, decoders 76 -78, elements 2ILI 79-81, one-oscillator 82, element 2I-NOT 83, second element 2И84, and element HE 85.

Control unit 3 is designed to output coded numbers to the output bus (second output 29) to control multiplexers 86 and 87 of calculator 4, to issue control signals on the bus (first output 24) to activate the output bus (first output 22) of accumulator 2 and output bus 23 block 5 in accordance with the program recorded in block 71.

The calculator 4 (FIG. 5) consists of the first 86 and second 87 multiplexers, the microprocessor 88, element 2I 89, element 12 OR 90, the design scheme for the end of the operation, consisting of the first element 91 of unilateral conductivity, f. the first load element 92, the first inertial element 93 and the element HE 94, the second load element 95 setting the frequency of the internal clock generator of the microprocessor, a chain consisting of the third load element 96, the second element of one-sided conduction 97 element 98 serving to set the microprocessor 88 to its initial state.

Jq

15 20

25 ed

| , 0

D5 D -155

35

The calculator 4 is designed to perform calculations on binary-decimal numbers, the recoded values of which are received from the input bus 31, -a also for issuing bit pulses to the bus 39, seven-segment codes to the bus 40, the signal corresponding to the number minus, and output 28 is the pulse of the end of the operation.

Unit 5 of parameter settings (FIG. 6) consists of eight programmable binary-decimal switches, SO-SO4 and four resistors 101 -101. The outputs of the switches 99 and 100 are connected in bit and form the output bus 23. The common terminals of the switches (1-8) serve to issue a single-code of one of the eight switches 99 and 100 to the bus 23 of the binary-decimal code.

Bus (output) 23 of unit 5 is combined with bus (output) 22 of drive 2. This is possible because amplifiers 66 are open-collector circuits. Through the wires of each of the tin 23 and 22 are connected bitwise, i.e. the younger with the younger, and the older with the older.

Decision block 6 (Fig. 7) consists of the first 102 and second 103 (single vibrators, first 104 and second 105 D-flip-flops, elements 2I 106-109. Single-oscillators 102 and 103 are pulse shorteners and are implemented on IC K561 LA7 according to a typical scheme.

The decision block 6 on the control signals arriving at the second 35 and third 36 inputs, and the sign signal arriving at the fourth input 37, outputs to the first or second outputs 45 or 46 signals corresponding to the directives to accept the batch or reject the batch .

The display unit 7 (Fig. 8) contains the first to the third blocks 110-112c of the first to the third indicators 113-115, item 2I 116, the first to the twelfth keys 1171-117, 118th, first 119 and second 120 amplifiers, counter 121, s first to twelfth seven-segment indicators 122-1226, 123-1236, generator 124. From the first output 19 of the display unit 7, the signal 51fi is sent to the first input 18 of the data input unit 1

data input, as well as to the third input 20 of the control unit 3, in which it carries out the installation of the trigger 68 in the zero state, which pauses the operation of the device.

The device works as follows.,

Before starting work, it is necessary to set switches 99-99 and 100-100 to the position required for the control process. For this, depending on the batch volume code and acceptance defect level, the parameters of the control plan H and B are determined.

On switches 99–99, a decimal four-digit N is dialed; on switches 100 -100, a decimal four-digit B.

Then, it is necessary to press the switch 55, which sets the counter to the zero state 64 JQ Continue monitoring if 0. After pressing the switch

53 at the output 16 of the data input unit 1 appears -signal Log.1, which is fed to the input 52 of the drive 2

j 5 and record increments

the current value of the number of i-suitable items in the counters 64 -64; besides, this signal from the output 16 of the block 1 enters the second input 17, the control block 3 and sets the RS-trigger 68 to one state (fig.9, point And block 3 controls).

The action of the switch is 54 analogs but, ep except that the signal

64 and 65-654 of drive 2, RS-flip-25 logical 1 appears on the first

68 and the counter 70 of the control unit 3 and the D-flip-flops 104 and 105 of the decision block 6.

In this case, the indicators 123-123 show zeros, the indicator 114, which displays the Continue Monitoring directive, is on, the indicators, 113 and 115, which display the directives, respectively, Batch and Reject

thirty

The output 10 of the data input unit 1 and, after entering the input 11 of the storage device 2, records the increment of the current value of the number of defective items z into counters 65 -65.

At the output of element 2I 69, the signal Log.1 appears (FIG. 9E), because at the second input of element 2I 69, a logical signal is also present. Log.1, since the one-shot 82 is not activated. This is obtained because the preceding zero state of the counter 70 supplies to the address inputs of the node 71 a zero address at which the data outputs are set to the state, which corresponds to the initial one.

party

not hot t.

The device is ready for operation.

From the production batch, one unit of production is successively selected. After checking each unit of production, the controller presses one of the switches 53 or 54 p of data input unit 1 depending on the result of the control.

z - the number of defective

units of production after the next control. The device ignites the indicator 113 - Take a batch, if U-2XbO, ignition of the indicator 115 - Reject the batch, if the ignition of the indicator 114 Continue monitoring if 0 .. After pressing the switch

53 at the output 16 of the data input unit 1 appears -signal Log.1, which is fed to the input 52 of the drive 2

and records the increment

the current value of the number of i-suitable products in the counters 64 -64, in addition, this signal from the output 16 of the input unit 1 is fed to the second input 17, the control unit 3 and sets the RS-trigger 68 to one state (Fig.9, point A unit 3 controls).

The action of switch 54 is similar, ep except that the signal

logical 1 appears on the first

0

five

0

The output 10 of the data input unit 1 and, arriving at the input 11 of the storage device 2, records the increment of the current value of the number of defective items z into counters 65 -65.

A signal from Log 1 appears at the output of element 2I 69 (fig.9E), since the second input of element 2I 69 also contains a logical signal. Log.1, since the one-shot 82 is not activated. This is obtained because the previous zero state of the counter 70 supplies to the address inputs of the node 71 a zero address at which the data outputs set the state to the source one.

Bits D7 and QA are controllers.

Depending on the state of bits

Switch 53 is pressed then, D7 and D8 there are four modes when the unit of production checked is suitable, switch 54 is when the unit of production tested is defective.

The device, after each press of switch 53 or 54, calculates the value

bots. The state when D7 1, D8 1 corresponds to the original, i.e. This is when nothing happens in block 3 of the control. Signals Log.O are present at outputs 5Q of the decoder 76 O - 2, which closes element 2I-2I-OR 72 through inputs AND, thus, bus 29 signals from outputs D1-D6 of node 71 and converter 75 of codes are not passed. 30 signal Log.1 is present, which prohibits the operation of multiplexers 86 and 87 of the calculator 4, and hence the operation of the microprocessor 88.

U H and B

(H + i) - (B-z),

(ABOUT

control plan parameters „

-the number of suitable units of production after the next control,

D7 and D8 there are four modes of operation. The state when D7 1, D8 1 corresponds to the original, i.e. This is when nothing happens in block 3 of the control. Signals of Log.O are present at the outputs of the 76 O-2 decoder, which closes element 2I-2I-OR 72 through inputs AND, thus, bus 29 signals from outputs D1-D6 of node 71 and converter 75 of codes are not passed. there is a signal from Log.1, which prohibits the operation of multiplexers 86 and 87 of the calculator 4, and therefore the operation of the microprocessor 88.

At the outputs of the decoder 77, the signals Log. O are present, because at its input enable V from the output of element 2I-NOT 83 the inhibitory signal Log. O arrives. The state, when D7 - O, D8, corresponds to the first operating mode of the device. In this case, at the output of 1 deshi b16193138

Log.1. The positive edge of this signal, the counter 70 switches to the next state, thereby changing the address of the node 71.

Suppose that at this address in the node 71 recorded data D1-D6, in accordance with which must be carried out as an arithmetic

RATOR 76 there is a signal Log.1, p. operation, which corresponds to the first

15

20

25

thirty

which permits the passage of data / f of node 71 D1-D6 through element 2I-2Y-ILY 72 to the input of multiplexers 86 and 87 of calculator 4. This mode allows performing arithmetic operations and entering constants, i.e. all the actions that microprocessor 88 can implement,

Data code D1-D6 defines the type of operation.

The state, when D7 - 1, D8 - O, corresponds to the second operating mode. Signal 1 is present at output 2 of the decoder 76, which enables the decoder 78 to work and at one of its outputs 0–13, the signal of signal 1 appears, which allows sampling of one of the switches 99, 100 of the parameter input block 5 or counters 64, 65 drive 2 and feed the binary-decimal code to the input bus 21 of the control unit 3. Through the code converter 75, the converted binary code is fed to element 2I-2I-OR 72 and then from output bus 29 to input of multiplexers 86 and 87 of calculator 4. This is used to enter control parameters and variables into microprocessor 88 from input unit 5 parameters and storage device 2.

The state, when D7 O, D8 O, corresponds to the third operating mode, in which the condition is checked, when the output of the O decoder 77 is the signal of Log.1, the condition U-2XSO, when the output 1 of the decoder 77 The signal Log appears, 1 and when Log.1 appears at the output 2 of the decoder 77, which corresponds to the end of the next monitoring cycle. In this case, the signal Log.1 passes through the elements 2ILI 81 and 80 and carries out the installation of the RS-flip-flop 68 and the counter 70. h

We will continue the consideration of the operation of the device from the moment when the output of element 2I 69 appears

35

40

50

55

operating mode. In this case, D7 O, D8 1.

At output 1 of the decoder 76, the signal Log.1 appears, which permits the passage of data D1-D6 through element 2I-NOT 72 via bus 29 to the input bus 31 of calculator 4.

At the output of element 2IL 79, a signal Log appears, 1 (Figs. 9 and 3), preparing element 2I-NE 83 for issuing a gate signal at output 30.

The signal Log.1 from the output of element 2I 69 enters the delay circuit, at the output of which this signal appears after 6 ms (Fig.9).

From the output of the delay element 74, the signal Log.1 is fed to the second input of the element 83 of the 2I-NO circuit. The output of the element 83 is the signal of the Log. O (Fig. 9K), which is fed to the output 30 of the control unit 3 and to the input 32 of the calculator 4.

Bidirectional multiplexers 86 and 87 switch the corresponding output of the phase-pulse-coded bit signals to the corresponding control input of the microprocessor 88 in accordance with the code on the address inputs of the multiplexers 86 and 87, which allows the microprocessor 88 to perform arithmetic or input operations. Microprocessor 88 stops issuing seven-segment codes for the duration of the operation, and then resumes.

This moment is shown in Fig. 9B at the output of element 12ILI of calculator 4. At the input of element 90, 12 phase-impulse discharge signals MT 88 are received.

In order to organize the cyclical operation of the microprocessor LSI, it is necessary to allocate the moment of termination of the operation, the minimum duration of which is 10 ms. For this purpose, serve the load element 92, the inertial element, carrying out the integration of the incoming signal. Chain parameters: R 10 kPm, С

operation that corresponds to the first

five

0

five

thirty

ds

35

40

50

55

operating mode. In this case, D7 O, D8 1.

At output 1 of the decoder 76, the signal Log.1 appears, which permits the passage of data D1-D6 through element 2I-NOT 72 via bus 29 to the input bus 31 of calculator 4.

At the output of element 2IL 79, a signal Log appears, 1 (Figs. 9 and 3), preparing element 2I-NE 83 for issuing a gate signal at output 30.

The signal Log.1 from the output of element 2I 69 enters the delay circuit, at the output of which this signal appears after 6 ms (Fig.9).

From the output of the delay element 74, the signal Log.1 is fed to the second input of the element 83 of the 2I-NO circuit. The output of the element 83 is the signal of the Log. O (Fig. 9K), which is fed to the output 30 of the control unit 3 and to the input 32 of the calculator 4.

Bidirectional multiplexers 86 and 87 switch the corresponding output of the phase-pulse-coded bit signals to the corresponding control input of the microprocessor 88 in accordance with the code on the address inputs of the multiplexers 86 and 87, which allows the microprocessor 88 to perform arithmetic or input operations. Microprocessor 88 stops issuing seven-segment codes for the duration of the operation, and then resumes.

This moment is shown in Fig. 9B at the output of element 12ILI of calculator 4. At the input of element 90, 12 phase-impulse discharge signals MT 88 are received.

In order to organize the cyclical operation of the microprocessor LSI, it is necessary to allocate the moment of termination of the operation, the minimum duration of which is 10 ms. For this purpose, serve the load element 92, the inertial element, carrying out the integration of the incoming signal. Chain parameters: R 10 kPm, С

 0.32 μF. Element 91 has a heel for fast recovery of a negative signal edge (FIG. 9B).

On Fig.9G shows the generated pulse, a positive front of which carries information about the end of the operation. This impulse from the output 28 of the calculator enters the input 27 of the control unit and the input of the element 2I-2I- OR 73, and from its output - to the input one. a vibrator 82, which is triggered by a positive pulse front (FIG. 9D). Pulse duration, 10

The cash enters the counting input of the counter 70 and increments its content unit by a positive front (Fig. 9E, time t.). For the sake of clarity, the timing diagram (Fig. 9, time points) shows the generation of two subsets of control signals at the outputs 33 or 34 of the control unit, i.e. when the device twice turns to the third operating mode.

The content of the node, 71, corresponding to the next address, is such that

operated by a single vibrator 82, equal to D7 D8 O. At the exit O decrypt20

thirty

at 12 x Tp 5 ms and is chosen so that the microprocessor 88 has completely finished generating the result.

The pulse from the output of the one-shot 82 arrives at the second input of the element 2I 69, from the output of which this pulse goes to the input of the counter 70. The positive edge of the pulse triggers the counter 70 by incrementing its contents by one - 25 (FIG. 9E).

To the input node 71 from the output of the counter 70 receives the following address. The control bits of ROM D7, D8 are implemented, one of the three operating modes. When the first two operating modes are implemented, the operation of the device is similar to that described.

Let us now consider the transition to the third operating mode, which is characterized by the fact that in this mode, verification operations are carried out.

The control bits D7, D8 of the ROM 71 are zero. At output O of the decoder 76, a signal Log.1 appears (FIG. 9I), which permits the passage of the signal from the output delay element 74 through element 2I-2I-OR 73 (FIG. 9G), time tЈ.

The signal from the output of element 73 by a positive front triggers a single-vibrator 82. The signal from the output of the one-shot 82 (fig.9D) is fed to the input of element 2I84, from the output of which the strobe signal goes to the enable input of the decoder 77 (fig.9L). The decoder 77, depending on the data at its information inputs, outputs to its outputs one of the control signals for checking or stopping.

The signal from the output of the one-shot 82 is also fed to the second input of the element 2I 69. From the output of the last cigor 76 there is the Log again. element 2I 84 - again prepare -; flax to allow the passage of the signal from the output of the delay element 74 at the time t4 (fig.9D), the 82 vibrator 82 generates another pulse which passed through element 2I69 causes the next increment of the counter 70 (fig.9E) at the time t

Suppose that the new content of node 71 corresponding to the next address is such that D7 1, D8 O, which corresponds to the second operating mode. The output 2 of the decoder 76 has a signal Log.1, which allows passage through element 2I-2I-OR 72 to the output 29 of the signals from the output of the converter 75 codes. The signal from the output 2 of the decoder 76 also enters the gate input V of the decoder 78, at one of the outputs of which O - 13 the signal of Log.1 appears.

From the output 24 of the control unit 3, the signals from the decoder 78 are fed to the input 25 of the accumulator and the input 26 of the sensor 5 of the parameter settings. On the bus 21 of control block 3, the code of the selected parameter-, e pa H, B or variables i, z appears.

At the output of element 2IL 79, the signal Log.1 appears (Fig. 93), preparing element 2I-NE 83 for passing the signal from the output of delay element 74 (Fig.9G).

When these signals coincide in time at the output of element 2I – NE 83: a strobe signal appears (FIG. 9 K), which from output 30 goes to input 32 of calculator 4.

Multiplexers 86 and 87 of calculator 4 make the connection to co. according to the calculator code of control inputs, with pulse-phase 35

40

50

55

The cash enters the counting input of the counter 70 and increments its content unit by a positive front (Fig. 9E, time t.). For the sake of clarity, the timing diagram (Fig. 9, time points) shows the generation of two subsets of control signals at the outputs 33 or 34 of the control unit, i.e. when the device twice turns to the third operating mode.

The content of the node, 71, corresponding to the next address, is such that

 D7 D8 O. At the exit About decrypt20

thirty

25

Rattor 76 Log is present again. element 2I 84 - again prepare -; flax to allow the passage of the signal from the output of the delay element 74 at the time t4 (fig.9D), the vibrator 82 generates another pulse, which passed the element 2I69 causes the next increment of the counter 70 (fig.9E) at time t

Suppose that the new content of node 71 corresponding to the next address is such that D7 1, D8 O, which corresponds to the second operating mode. The output 2 of the decoder 76 has a signal Log.1, which allows passage through element 2I-2I-OR 72 to the output 29 of the signals from the output of the converter 75 codes. The signal from the output 2 of the decoder 76 also enters the gating. the input V of the decoder 78, on one of the outputs of which O - 13 appears the signal of Log.1.

From the output 24 of the control unit 3, the signals from the decoder 78 are fed to the input 25 of the accumulator and the input 26 of the sensor 5 of the parameter settings. On the bus 21 of control block 3, the code of the selected parameter-, e pa H, B or variables i, z appears.

At the output of element 2IL 79, the signal Log.1 appears (Fig. 93), preparing element 2I-NE 83 for passing the signal from the output of delay element 74 (Fig.9G).

When these signals coincide in time at the output of element 2I – NE 83: a strobe signal appears (FIG. 9 K), which from output 30 goes to input 32 of calculator 4.

Multiplexers 86 and 87 of calculator 4 make the connection to co. according to the calculator code of control inputs, with pulse-phase 35

40

0

five

discharge outputs. The microprocessor 88 stops issuing seven-segment codes and performs an input operation (Fig. 9B).

The generated pulse from the output 28 of the calculator 4 (Fig.9G) is fed to the element 2I-2I-OR 73. The signal Log.1 from the output of the element 73 enters the input of the one-shot and starts it (fig.9D, time tg).

The pulse from the output of the one-shot 82 is fed to the second input element 2I 69, the signal from the output of which goes to the counting input of the counter 70 and causes an increment of its contents by one (FIGS. 9E and B, time t.,).

The contents of the memory node corresponding to the next address are now such that D7 D8 O. At the output O of the decoder 76, there is a signal Log.1 (FIG. 9I).

The signal from the output of the delay element 74 changes its state from Log.O to Log.1 (Fig. 9G) and is fed to the input of element 2I-2I-OR 73 from the output of which the signal goes to the input of the one-shot 82 and positive edge of the signal triggers it. (fig.9D). The negative front of the signal from the output of the one-shot 82 is fed to the input element 2I 84, from the output of which the signal is fed to the gate input of the decoder 77 (fig.9D). The mode in question is the third operating mode, and it is expected that a control termination signal is generated. In this case, the output of the decoder 77 is the signal Log.1, which is fed to the input of element 2ILI 81, from the output of which the signal of Log.1 is fed to the input of setting to the zero state - the original counter 70 and to the input of element 2ILI80 , from the output of which the signal Log, goes to the R input of the RS flip-flop 68 and sets it to the zero state (FIG. 9D).

The node / 71 outputs to the control outputs D7, D8 a signal of Log.1, which causes the appearance of the signal Log.O at the output of the decoder 76, and therefore, at the output of element 2I 84, the signal Log.O appears (Fig.9I and L).

The signal from the output of the one-shot 82 enters the input element 2I, 69, but now the element 2I 69 is closed for passing a positive edge

0

five

0

five

0

five

0

five

0

five

This signal from the output of the one-shot 82 because its second input is the signal Log.O.

The operation of the circuit is suspended. The microprocessor 88 continues to generate seven-segment codes, providing an indication on the indicators 122-122 of the current result of the next control act, in this case (U-2H).

Consider the work of the decision block 6.

In accordance with the control program recorded in the node 71 of the control unit 3, the device step by step calculates formula (1). When at a certain step, namely, at 20, the MP 88 performs the calculation of the value of U, at the 21st step, the output of the decoder 77 O signal 77 appears. The condition test signal U Ј 0.

I- The first bit-phase pulse signal, together with one of the segment signals at the outputs of the microprocessor 88, determines the sign of the result of the calculated value, with the first signal overlapping with the second. The duration of the first 400 µs, and the second 300 µs. If there is a minus sign, a positive impulse appears at the output of element 2I 89 of calculator 4.

In the presence of a positive number or zero, the output signal of the element 2I 89 is missing. Therefore, it is difficult to verify directly.

To implement the condition check U 0, the equivalent check (s) e: 0 is performed. A change in the sign of the number is made in advance in the program.

The second input 35 of the decision block 6 receives the signal Log.1 from the fourth output 33 of the control block J. This signal arrives at the first input of element 2И 106 and prohibits its operation for the entire duration of the signal. The first two positive impulses correspond to the duration of the condition test impulses (FIG. 9L).

This signal is fed to the input of the one-shot 102, from the output of which a short positive pulse sets the D-flip-flop 104 to the one state, since it is preliminarily set to the zero state by the first input 15.

test is performed - check of condition (-U) 0.

The fourth input 37 of block 6 receives a minus sign impulse from the second output 38 of the calculator 4.

If the minus sign is absent at the input of the element 2I 107, the positive impulse of the sign for the duration of the condition test pulse is absent

The trigger 104 will retain its one state and upon termination the signal at the second input 25 at the output of element 2I forms the signal Log.1 which corresponds to the condition (-U) 0, i.e. -UЈ0. |

If the minus sign is present at the input, then from the output of element 2I 107, a positive impulse is sent to the counting input of trigger 104 and sets it to the zero state, since the Log.O. signal is constantly present at its D input.

Upon completion of the test signal at the second input 35, at the output of element 2I 106, a Log.O signal is generated, which corresponds to the condition (-U) Ј0, etc. U s O.

The signal Log.1 from the second output 46 of the decision block 6 enters the input 44 of the display block 7 and causes the indicator 115 to light up and the indicator 114 goes out.

At the output of element 2I 116, the signal Log.O appears, which is fed to the third input 18 of data input unit 1. Elements 2I 61 and 62 are blocked and not

pass signals from elements 2ILI 58 and 60. This is done in order to exclude accidental operator actions to preserve the result.

In addition, the signal from the first output 19 of the display unit 7 is supplied to the third input 20 of the control unit 3, which causes the RS-3 generator 68 to be set to the zero state, which stops the operation of the control unit. The indicators of the display unit 7 show the value (-U)

The operation of the second part of decision block 6 is similar to that described. The condition test signal () O is generated at step 32 of the program and

arrives at the third input 36 of the block 6 of decision making from the fifth output 34 of the control block 3. This is where the verification of the condition (i-2H) e,

therefore, it is not necessary to pre-change the sign of the expression in brackets.

If the condition is fulfilled, a signal Log.1 appears on the first output 5 of the ruling unit 6, which arrives at the third input 43 of the display unit 7 and lights up the indicator 113, while the indicator 114 goes out.

The entire program recorded in the control node 71 is 33 steps and is shown in the table.

f5

20

25

thirty

ty

„.“ Ty

ds

G (,

35

50

H

"L

H

one

R

five

+ (-U) fc o

defect counter Input low-order defect counter Multiply

Enter the highest bit of the parameter B

Enter the third bit of parameter B

Enter the second bit of parameter B

Enter, the low-order bit of parameter B

Enter the highest bit of the parameter H

Enter the third bit of the parameter H

Enter the second bit of the parameter H

Entering the low-order bit parameter H Rec.

Enter high bit. counter of suitable products Input of the third digit of the counter of suitable products Input of the second bit of the counter of suitable products Input of the younger digit of the counter of suitable products. Add, Check condition, if Yes, then reject the party Brackets open

Table continuation

Yes, take a party

the end

The use of a device for input control of products using a consistent control plan allows for an increase in the controller’s labor productivity, since it significantly reduces the number of product tests until a decision is made to make or cast a batch compared to single-stage and two-stage control plans (2-fold compared to one-stage). . Therefore, the controller can control a large number of batches.

Subjective errors of the controller are excluded, inasmuch as even an omission in the inspection of products cannot affect the accuracy of decisions, since the directive instruction Continue monitoring indicates to the controller the need for further monitoring until the device makes a certain decision.

At the same time, under normal control plans, the controller’s subjective errors may lead to an incorrect result due to omissions in the control of incorrect counting of fit or useless items, etc. The organizational complexity of the multi-stage control plan is also removed, since it comes down to simply pressing the Marriage or Goden buttons. . .

The reliability of the control is increased due to the fact that the operator has the opportunity to observe the progress of the control process. In the process of control, the operator successively repeatedly presses the switch 53 - Go

0

five

 switch 54 Rejection block data. ,

Assume that the indicator 114 is on in the monitoring process. Continue monitoring of the display unit 7. After each control act, the device at step 32 calculates the expression (and-2H). And after the end of step 33, the indicators

The Q of the display unit 7 shows this value.

 Let us also assume that H 50, B 50. In this case, according to formula (1), the expression (TJ-2H) takes, consequently, after each act, the control of a number of numbers differing by one;

49, 48, 47 ,, .. If there are no defective products, the sequence of numbers decreases in absolute value and at (U-2H) the indicator 113 of the display unit 7 lights up, which corresponds to the directive Take Party.

The operator has the opportunity to observe the process of control. On any control act, it is also possible to verify numerically the reliability of the control by the formula (1), since the values of H, B are typed on the switches 99 and 100 and are visually observable, the indicators show the values, i and z

If in the process of checking products a defective unit was encountered, then according to formula (1), for example, on

35 third control act, expression

(U-2H) is 98, instead of 47, i.e. there is a jump in values, which draws the operator’s attention to the fact that a definite directive may soon be reached, in this case Block a Party, since in this case U 2 is close to zero.

If the development of the directive Block a batch was made, the indicator 115 is lit, then on indicators 117 the actual value of the U value is displayed. The operator also has the ability to numerically check the result of the control. In addition, the monitoring process is blocked by sending a signal Log.O from the first output 19 of the display unit 7 to 55 third input 18 of the data input unit 1. Improving the reliability of input control is essential because the error in the development

45

50

Certain directives may result in acceptance of a batch clogged with defective products, and vice versa, the transfer of the batch meets the established requirements.

Lots of products can contain, tens of thousands of products, which lead to unjustified: a lot of people lost, and the counter-lolity of responsibility,

The reason for noting is the relative simplicity of the device, since the compilation of the program is 1; TC; in practically natural language, the maxima are approximate for Gmgln not prepared by the GPU.

Claims (1)

Formula and b about b re e P g and one . A device for input, ongroup products containing blot data entry, a drive, a block of responses and a parameter setting setter, whose data inputs are device data inputs, other than cgp, in order to increase the reliability and performance of the device} it has a control unit, a control plan module and a display unit, the first and second installation outputs, the control plan calculator output, and the first control unit data output are connected to the first and second settings to the inputs of the decision block, to the input of the gateway to the data input of the control plan calculator, the second data output of the control block is connected to the first data inputs of the accumulator and to the data input of the sensor of the parameter settings, the data output of which and the data output of the accumulator are connected to the input dacha parameter code of the control unit, the output of the installation of the data input unit is connected to the installation input of the control unit, the outputs Goden and Scrap - to the accumulator inputs of the same name, the output of the Voly reset to the accumulator inputs of the same name, control unit and and the decision unit, the output end of operation control plan calculator is connected with the same input of a control unit, an output ONER Star "yes u 1 - with the same input decision unit, the first and second outputs da Shikh - with the appropriate PDP-1 the second and the second inputs are connected to the display, which is available at the gate of which is connected to the one-way output of the rogiepi block. vr, - UOD of general blocking of work jrrpofi- tvl - h to the inputs of the occlusc rk to t, gift and input i, output to the co rs at 1READING of the fuse itto & - - to the second input, from at the pit, second VOD UOD data which it is united with the name of the display unit. j-str of guyu p. one about hl and f5 0 five 0 five WITH five 0 five vat, moreover, To the unit of the decision making, the second and the second D-triggers, 1st c. TI and the second D-triggers, from the first five-worn elements of 2K, are: cf. of elements 2I of the owner - of the section of the Sokhotsi Sotoy and the outputs of Marriage and H den Slok, respectively, the arms of the first hour of the second elsmetosis 2I are 1 1 st the camp, which will be built: through the first single bioretor it is connected to the installation; vhg house of the first D-trigger,,; synchronization and xo / fOM of the connected connected respectively to you, one of the second element 2I and to the bus of the device potential zero, the second year ji the first input is the input of the unit 2I, the second input of the fourth and the first the input of the third element 2I is the sec / installation input of the device, which through the second one-way vibrator to the secondary input of the second D-flip-flop, is synchronized and input to the input, respectively, to the output of the Ego element 2I and to the steering tire, mustache roystva, the outputs of the first and the second ti-griggerov ssepineny sopt- etstveng about a second vhodschchi first and third elements 2I. 3. The device according to claim 1, wherein the control unit includes an RS flip-flop, element 2I, a binary counter, a fixed memory node, the first and second you 2I-2I-IL11, the element stutter - the originator of the codes, from the first to the third designators, from the first to the third elements of the 2NLI, one-one, element 2I-PE, the element b. . NOT, setting input Rc, -Tpnv i cm, input of control panel K (och, no- B: t НХО1-, element 2И- 2П- I jIII, j - -, 41. and the first input of the third element 2IL is set, the parameter code, blocking and master reset by the block inputs, respectively, the output of the third decoder, the output of the first element 2I-2-OR, the first and second outputs of the decoder, the output of element 2I-NOT are the first and second data outputs, the first and second installation and gating outputs of the block, respectively, the RS-flip-flop output is connected to the first input of the first element 2I, the output connected to the first input of the binary counter and through the delay element to the second inputs of the second element nta 2I-2I-OR and to the first input of the element, the second input of which and the third input of the second element 2I-2I-OR are connected to the output of the second element 2IL, the output of the third element 2IL or connected to the first input of the second element 2IL or to the reset input of the binary counter code the element is NOT connected to the second input of element 2IL, the output connected to the Reset RS input is three meters, the outputs of the binary counter are connected to the address inputs of the node by-1 with the memory, the outputs connected to the first group of inputs of the first element 2I-2I-OR to the decrypt data inputs first to third, the outputs of the code converter are connected to the second group of inputs of the first element 2I-2-OR, the first output of the first decoder is connected to the first input of the first element 2IL, and the first input of the first element 2I, -2I-OR, the second output the first decoder is connected to the second input of the second element 2ILI, to the second input of the first element 2I-2I-OR, to the input gate of the third decoder, the third output of the first decoder is connected to the fourth input of the second element 2I-2I-OR and to the first input of the second element 2I, out House connected to a strobe input of the second decoder, a third output connected to the second input of the third element 2 or, the output of the second element 2I-2I-OR via odnovibrato coupled to second inputs of the first and second elements 2I. 52 l-ver s Fiyo.2 22 67 SO & Fig.Z Fyu.4 32 96 97 Phage. five 96 §If dfp 9 Ј2  IL CIC6I9I