SU1672415A1 - Clock period pattern-based automatic control and debugging system - Google Patents

Abstract

The invention relates to computer technology and automation and can be used in machine control systems, in particular, in automation systems for design and commissioning works in the design and manufacture of equipment with a cycle mode of operation. The purpose of the invention is to optimize the programming and fault diagnosis process. To achieve this goal, the group of OR elements is additionally introduced into the system of automatic control and debugging, which allow to take into account the state of the sensors of the state of objects, which have an uncertain state in a step, two subtractors, which allow to determine the numbers of such sensors that have a different from the programmed one, and determine the outputs included in this particular cycle, the OR-NOT element, which takes into account the presence of unprogrammed sensors in the cycle, the register 11 for storing the previous cycle, i.e. the state of the outputs, the switch 13, which allows to generate and transmit to the indicator 14 all the information about the input signals, the reprogramming device, which, in the image of the sequence chart, enters the data into the program storage unit. 6 Il.

Description

The invention relates to computer technology and automation and can be used in machine control systems, in particular, in automation systems for design and commissioning works in the design and manufacture of equipment with a cycle mode of operation.

The purpose of the invention is to optimize the programming process and diagnose faults.

FIG. 1 is a block diagram of the proposed system; Fig 2 shows an example implementation of a programming device; in fig. 3 is an example of a tactogram of a control object of three mechanisms; FIG. 4 shows this clock pattern made on

alphanumeric video terminal device, fig. 5 shows a digitized image of a sequence chart, fig. 6 shows a data area of a program block corresponding to masked inputs.

The automatic control and debugging system contains a pulse generator 1 in series, an AND 2 element and a pulse counter 3, as well as a program storage block 4, a group of And 5 elements of an object state sensor 6, a block of 7 elements

Os vj

Yu Ј

cl

OR, EQUIVALENCE elements 8, the first subtraction unit 9, the element OR NOT 10, the previous clock storage register 11, the second subtraction unit 12, the indication signaling switch 13, the indicator 14, the reprogramming device 15, the interface connection 16. The program storage unit 4 represents It is a matrix storage device. The rows of the matrix are divided into separate areas in accordance with the purpose: area of data on the state of the outputs (on or off); input status data area (on or off); separate from (the rock for the signal about the end of the cycle (the last cycle of the cycle); the data about the masking of the sensor signals (the unspecified state of the sensor in this cycle) and the data about the sensors for switching to new cycles. The outputs of block 4 of the programs are the outputs of the lines above data areas. The column number of the matrix connected to the outputs is determined by the information on the input of program block 4. Moreover, the column numbers of the matrix correspond to the state numbers of the counter 3 and the tact numbers of the control object. 7 OR elements contain a set of two-input OR elements. The first inputs of the elements are connected to the program storage block 4, and the second to the outputs of the respective sensors 6. When masking the signals from sensors 6, a single signal is observed at the first input of the OR element, i.e. any signal from the sensor 6, at the output of the OR element, there is a single signal. At a zero signal at the first input of the element OR, the output signal corresponds to the signal of the sensor 6. Blocks 9 and 12 of the subtraction contain diagrams of the bitwise subtraction of the signals of the first inputs from the signals v the inputs (i.e. no loan from senior bits). The switch 13 serves to generate and transmit information on the input signals to the indicator 14. Accordingly, when the zero signal at the control input, which is connected to the output of the OR-NOT 10 element, information is transmitted from the outputs of the first subtraction unit 9, and for a single signal, from the outputs of the second subtraction unit 12 and EQUIVALENCE elements 8. Transmission of information from the outputs the counter 3 to the indicator 14 is carried out by the switch 13 permanently and is independent of the signal at the control input. Additionally, the switch 13 transmits the signals of the sensors 6 indicated in the indicated information from the outputs of the EQUIVALENCE 8 elements or the first subtraction unit 9. Switch 13

can be performed on the basis of logical elements AND and OR. The reprogramming device 15 comprises a control computer 17, which is interfaced with

a video terminal device 18, a memory device 19 programs and a memory device 20 tactogram. In addition, the control unit 21, the address generation unit 22, and

0 block 23 decryption. The outputs of the blocks 21-23 are entered in the communication block 24. Moreover, the outputs of the decryption unit 23 are entered into the communication unit 24 through intermediate status registers: the output status register 25, the input state register 26, the mask register 27, the register 28, the indication of the cycle switching sensors and the cycle termination signal register 29. The output of the device 15 is the output of the communication unit 24: it is interfaced with the interface 16 with the program storage unit 4.

The system works as follows. Before starting work on the debugging of the control object by the tactogram (see Fig. 3) on

5, the screen of the video terminal 18 reproduces the image of the tactogram (see FIG. 4). In this case, the conventions are

- - the input specified at the beginning of the line

0 this cycle is included:

... - the input specified at the beginning of the line is masked in this cycle (i.e., its state is indefinite and is not taken into account); - the entry specified at the beginning of the line

5, this cycle switches on and switches the cycle to a new cycle, the output indicated at the beginning of the line is on;

   - the input and output indicated at the beginning of the line are included;

0k - the end of the cycle

the space corresponds to the off state of the inputs and outputs.

After reproducing the tactogram control computer 17

5 transfers information (digital recording) about the input image from the memory of the video terminal device 18 to the storage device 19 of the storage programs. Then it is written line by line but into the memory device 20 of the tactogram as follows. In the first cell of the line, machine 17 writes the number of the input (the serial number of the sensor is 6). in the second memory cell output number

5 (the serial number of the second element is 5). In subsequent cells, the digital reference code is entered, i.e. the third cell is entered by the code of the symbol of the zero cycle, in the fourth cell the code of the first cycle and further. For example, if the symbol ... has code 1, designation - code 2 and, accordingly, code 3, code 4, k - code 5, and space - code 0, then the image of the tachogram (see Fig. 4) corresponds to the digitized image (see Fig. 5) in the memory device 20 of the tachogram Control unit 21 synchronizes the work between the control computer 17 and the communication unit 24, and then, via the interface connection 16, with the program storage unit 4. To do this, at the command of the control unit 21, the control computing machine 17 reads sequentially data from the rows of the storage device 20 and transmits it to the address generation unit 22 and decryption fleas 23. In the address generation unit 22, the numbers of the input and output from the first and second cell of the line are stored. The decryption unit 23, in accordance with the received data, writes single signals to the registers 25-29 when the data matches, and zero signals if it is different. Thus, single signals are recorded in the register 26 of the state of the inputs with the code (-), 3 () and 4 (). In register 27 masks with code 1 (...). In register 28, the switching sensors are indicated with code 3 (). And in the register 29 of the signal of the end of the cycle - with code 5 (k). After processing the data of the entire line, the control unit 21 issues a command to the communication unit 24 to overwrite the data from the registers into the rows of the storage matrix of the program storage unit 4. The address of the line indicates the address generation unit 22. For example, input No. 4 is indicated for the first row of the hologram (see Fig. 3), and output No. 3. Accordingly, the communication unit 24 overwrites the output status register from the state output register 25 into the third row of the output state data of the program unit 4. The data of registers 26-28 is written into the fourth lines of the corresponding data areas, and the data of the cycle ending register 29 is written into the data line about the end of the cycle. Further, as described above, the control unit 21 issues a command to process the next line and so on until the last line. In this case, in the program storage unit 4, all information, for example, information about the masking of inputs (see. Fig. 6), is recorded for further processing. After this, the control system is ready to work directly with the control object. To start an automatic cycle, the control object is reset to its initial state in accordance with the beat in the O tachogram. In this case, the outputs of the program storage unit 4 receive information corresponding to the zero column. The signals of sensors 6 through the masking scheme (block of elements OR 7) arrive at the elements EQUIVALENCE 8. Since the object is in the initial state, all signals correspond to the specified ones (except for the signal from sensor 6. determining the beginning of the automatic cycle). The element EQUIVALENCE 8 corresponding to the given sensor 6 receives a zero signal on the element AND 2. It prohibits the passage of the pulse of the generator 1 to the switching of the counter 3. Then the sensor 6 is switched on. This leads to a change of the zero signal to the unit one. The pulse of the generator 1 through the element And 2 switches the counter 3

5 to state 1. At the command of the counter 3, the program storage unit 4 outputs to its outputs the information recorded in the first column. After another element is the equivalence of 8 corresponding to the sensor 6

0 switching in step 2, fixes the mismatch of signals and generates a zero signal, which prohibits further switching of the counter 3. At the same time signals about the state of the outputs through a group of elements And

5 5 includes 1 outputs programmed in step 1. In the process of processing the command, the signals switch the named switching sensor 6 to beat 2. Counter 3 is set to state 2. And program block 4 outputs information from the second column. Again, the signals of the sensors 6 do not match the set, and so on in the cycle. Upon reaching the last clock cycle, the signal from the line exit about the end of the cycle

5 resets counter 3 and the cycle repeats. Simultaneously with the switching of clocks, the process of testing, namely, from signals from inverse outputs of elements, is controlled by an EQUIVALENCE 8 second block 12

0 subtraction subtracts the signals from the output of the program storage unit 4, i.e. Signals indicating which sensors 6 must have a non-equivalent state, as they are in this cycle, switch 6 sensors into a new cycle. It is also determined which outputs are included in this particular cycle. For this, the signal about the change of the state of the counter 3 is sent from the output of the element I 2 to the control input of the register

0 11. Register 11 receives and stores signals from block 4 of program storage, i.e. stores information about. which outputs were switched on in the previous cycle (before switching to the new one). Therefore, the first block 9 of the calculation, subtracting from the activation signals of the outputs from block 4 of the program storage (signals of the new cycle) the signals of the activation of the previous cycle, form the outputs of the unit signals corresponding to the outputs included in this cycle.

In this case, if the elements EQUIVALENCE 8 fix the discrepancy of only the programmed sensors 6, then the outputs of the second subtraction unit 12 are zero signals, and the output of the element OR NOT 10 is single. Under the influence of this signal, the switch 13 processes the signals from the outputs of the elements EQUIVALENCE 8 and the first subtraction unit 9. Indicator 14 reflects the numbers of inconsistent sensors b and the numbers of the outputs that the sensors 6 have to switch. Additionally, the switch 13 according to the signal from sensors 6 generates a message about the status of the sensors 6 being displayed (on or off) and the measure number, i.e. the malfunction is either a failure of the indicated sensors 6 or a failure of the indicated outputs. In case of a malfunction caused by an unplanned actuator stroke or a failure of sensors 6, EQUIVALENCE 8 elements detect a discrepancy between signals of unplanned, as switching, sensors 6. Accordingly, single outputs are observed at the outputs of the second subtraction unit 12, and at the output of the element OR NOT 10 the signal is zero. It prohibits issuing commands from the outputs of a group of elements And 5 to the control object, thereby preventing the situation from aggravating. The switch 13, on signals from the output of the second subtraction unit 12, transmits to the indicator 14 information about the numbers of the sensors 6, which fix the fault, and indicates their status. The technical and economic effect is to increase the functionality of the system. The introduction of block 7 of the elements OR makes it possible to disregard the sensors 6 having an indefinite state in a clock. The inclusion in the circuit of the second subtraction unit 12 makes it possible to determine the numbers of the sensors 6, which have a state different from the programmed one. The presence of unprogrammed sensors 6 in the clock cycle is taken into account by the introduction of the element OR NOT 10. The register 11 stores the previous state of the outputs, and the first subtraction unit 9 determines the outputs included in this particular clock cycle. The switch 13 allows the necessary information about the input signals to be generated and transmitted to the indicator 14. The programming device 15 in accordance with the image of the waveform enters data into the program storage unit 4. The use of the system significantly simplifies the procedure.

Claims (1)

programming and at the same time provide an indication of faults. Formula of the invention. Automatic control system and debugging based on the display of the clock diagram, containing a pulse generator, the output of which is connected to the first input, the element I. a pulse counter, a program storage unit, a group of elements AND, and also the object state sensors, an indicator and a unit of elements EQUIVALENCE, the group of direct outputs of which is connected to the group of element I, and the first group of inputs to the first group of outputs the program storage unit, the control output of which is connected to the pulse counter zero input, characterized in that, in order to optimize the programming and fault diagnostics process, the group of elements OR two subtractors, the OR-NOT element, the display signal switch, register are additionally entered into it storing the previous clock cycle and the reprogramming device, the output of which is connected via an interface connection to the input of the reprogramming device, and the second group of outputs of the program storage unit On the first group of inputs of the first subtraction unit and the group of information inputs of the memory register of the previous cycle, the third group of outputs of the program storage unit is connected to the first inputs of the OR elements of the group and its fourth group outputs - with the first group of inputs of the second subtraction unit, the outputs of the object state sensors, the second outputs of the first and second subtraction blocks, the group of inverse outputs of the EQUIVALENCE element block, and the output of the pulse counter and the OR element are NOT connected respectively to the group of information inputs of the display signals switch whose output is connected to the indicator, and the control input - with the output of the pulse counter, the output of the element I is connected to the control input of the record of the memory register of the previous cycle, the outputs of which are connected to the second group of the first subtraction unit, the outputs of the elements OR groups are connected to the second group of the EQUIVALENCE block of elements, the group of inverse outputs of which is connected to the second group of inputs of the second subtraction unit, the group of outputs of which is connected to the corresponding inputs of the element OR, the output of which is connected to the second inputs of the elements AND of the group FIG. 2 20 . 3 fig.C FIG. five FIG. 6