SU1413633A1 - Device for digital inspection of electronic circuits - Google Patents

Abstract

The invention relates to electronic and computer engineering and can be used in automatic control and diagnostic equipment for electronic components. The purpose of the invention is to increase speed. The device contains a block 1 of control, a block of 2 elements And, a block of 3 formed a test word, registers 4, 5, | 7 6, digital-to-analog converter 7, switching unit 8, comparison unit 9, analog-digital converter 10, input-output group 11, control result output group 12, control result readiness output 13, control input output group 14, start input 15, output 16 readiness to receive a test word, inputs 17 test words. The invention consists in using information about unchecked contacts stored in the test register to form a test word in such a way that bits of the test information from the external device are written to the bits of the test register corresponding to the contacts being monitored. the test, corresponding to unchecked contacts, automatically fit random values. A positive effect is achieved by inputting only meaningful test information. 2 hp f-ly, 3 ill. "00 a od & e

Description

The invention relates to electronic and computer engineering and can be used in an apparatus for the automatic monitoring and diagnostics of electronic components.

The purpose of the invention is to increase speed.

Fig, 1 shows the functional diagram of the device for digital control of electronic circuits; FIG. 2 is a functional block diagram of the formation of the test words in FIG. 3 is a functional block diagram of the control unit;

The device contains a control block 1, a block of 2 elements AND, a block 3 of forming a test word, registers 4-6, a general analog converter (D / A converter) 7, a block 8 switches, a comparison block 9, an analog-digital converter (L) 10, a group of inputs - outputs 11, a group of outputs 12 of the control, the output 13 of the control result readiness, a group of control inputs 14, a start input 15, a readiness output 16 of the test word and a group of information inputs 17.

Block 3 of the test word formulated (Fig. 2) contains a clock pulse generator 18, counters 19 and 20, switch 21, AND 22 element, OR element 23, shift registers 24 and 25, a group of information inputs 26, a group of information inputs 27 masks, an input 28 start-ups, mode setting input 29, group of information outputs 30, test word readiness output 31, and readiness output 32 of a part of the test word.

The control unit 1 (Fig. 3) contains the deshifrater 33, the OR element 34, the AND elements 35-37, the delay element 38, the first to the fifth outputs 39-43, the strobe input 44, the recording resolution input 45 and the group of information inputs 46.

The proposed device works as follows.

The device accepts compressed test information on input 17 and control information on input 14. The information is accompanied by a trigger signal received on input 15. The trigger signal unlocks counters 19 and 20 and register 25. This clears the reset, ready. receiving test words and information is recorded in the register 24 and the decoder ZZ. The piece of information rewritten into register 24 of block 3 is allocated to certain bits of the test word. For this, switch 21, controlled by counter 19, switches one after the other all bits of register 6 to one of the inputs of AND 22. The incoming state of AND 22, through switch 21, of the state of the corresponding bits of register 6 is gated by its pulse 5 generator 18 and, if it has a potential of 1, the pulse travels to the clock shift register 24. The same pulse from the generator 18 bits of test information from the output

0 I register 24 is rewritten by the input of the J sequential write to register 23. If the polled register of mask register 6 has the potential. O, the pulse for the register shift input 24 is not

5 passes, and the value of the test information bit at the output of the shift register 24 and the input of the register 25 does not change. Register 25 records information on the pulse from the generator.

0 18. The value recorded in register 25 corresponds to the value that the next controlled contact should have in the test word being formed,. the value of the output of the register 24. Since this value can be both zero and one, it is not possible to know in advance what will be written to the bits of register 4 corresponding to unchecked pins according to the contents of register 6 of the mask. But this is not a matter of principle, since this information is not used either for switching signals to the object of control, nor for comparing with signals taken

r from the object of control. Control over whether all the bits from the test information received into the register 24 were used to form a test word is carried out by a counter 20, the overflow output of which through the OR element 23 is used to form the ready signal of a part of the test word. The CLL and ADC establish the correspondence between the signal on the contact of the control object and the multi-digit binary code of its digital display, i.e. each contact of the control object in register 4 must correspond to several bits

0

five

31

code. This leads to the fact that each bit in registers 5 and 6 corresponds to several bits of register 4. Accordingly, the bit size of counter 19 must take into account the number of bits of register 4, Therefore, to control the switch 21, the lower bits of counter 19 are not used . This allows the overflow signal of the counter 19 to be used as a test word readiness signal, strobe the output signals of control unit 1 and participating in the formation of the readiness signal 32 to form part of the test word. The two sources of signal formation 32, combined by the element OR 23, determine the dual reason why the next test word formation cycle can be completed: when the next piece of test information is processed and you need to get the next one when the test word formation is completed and no further formation is required. (even if some bits were left unprocessed in shift register 24) The generated test word from the outputs of register 25 can be rewritten to the desired address determined by the control block events. The code of the recipient of the test word is determined by an external device and accompanies each piece of test information. This code is fed to the inputs of the decoder 33 with memory in the form of a register. The corresponding write signals to the receive registers are formed after gating the output levels of the decoder 33 by the signal 31 to complete the formation of the test word. At the output of the OR 34 element, a mode signal 43 is generated, which is fed to the input of the switch 21. If the signal 43 has a level 1, then the output of the switch 21 constantly has potential 1. This results in a sequential rewriting of all the test information from register 24 to register 25 without gaps and inserts. This mode is necessary when recording information in registers 5 and 6. For register 6 masks, all bits must be significant, since otherwise it is impossible to overwrite the configuration of unchecked contacts into it. For register 5 switching the same mode is necessary, since there are randomness of value written in the test 3633

A new word in known unchecked contacts, although they must all be switched by definition. At a write signal 39 to register 4, the test word from register 25 is written to register 4. The same write signal to test register 4 is fed to the input of delay element 38,

from the output of which the signal 41 is prepared. READINESS of the control result. The information from the test register goes to the DAC 7, at the outputs of which the levels determined by

5 input test codes. Formed DAC 7 (for each contact separately) levels are fed to the inputs of the switching unit 8, which, depending on the mode of operation

0 with the input-output 11 of the control object, which is determined by the state of the corresponding bit of the switching register 5, either switches the received level to the input of the control object, or blocks its passage. In any case, the signal level present at the input-output of the control object (switched or not) is converted by the ADC, into the code

Q is compared in comparison block 9 with the code stored in test register 4. After masking on the block, elements AND signals related to unchecked pins are outputted at output 12 of the device.

Claims (3)

1. A device for digital control of electronic circuits comprising a control unit, first and second registers, a digital-to-analog converter, a comparison unit, an analog-to-digital converter, and a switching unit, the group of control inputs of the device connected to the group of address inputs of the control unit, the first and second outputs of which are connected to the recording inputs of the first and second registers, respectively, the group of outputs of the bits of the first register is connected to the group of inputs of the digital-analog converter, the group of outputs to torogo connected with the group of information inputs commutator tion unit, a group of control inputs of which is connected with the group of output bits of the second register, a first group of information inputs srav0 block 0 is connected to an analog-to-digital converter output group, whose input group is connected to a switching unit output group and is an ipoftcTBa group of inputs / outputs for connecting to a controlled-circuit input-output group, in order to improve speed : roystva, a test word formation unit; a third regis- ter: a hyster and an AND element block are entered into it; the third output of the control block is: with the output of READINESS of the control device, the output group of the control result The first is connected to a group of outputs, a block of elements. And the fourth output of the control block is connected to the recording input of the third registrar, the group of information inputs of which are combined with the group of information inputs of the first and second registers and connected to the group of information outputs of the test word generation, the group of information inputs of the mask of which is connected to the group, the outputs of the bits of the third register and the first group of inputs of the block of elements I. the second group of inputs of which is connected to the group of outputs of the block cf The second group of information inputs of which is connected to the group of outputs of the bits of the first register, the strobe input of the control unit is connected to the readiness output of the test word of the test word generation unit, the readiness output of part of the test word of which is connected to the write enable input of the control unit and is ready output receiving a test word of the device, the group of information inputs of which is connected to the group of information inputs of the block forming the test word, the start input of which Is the start input of the device, the input of the setting of the mode of the forming unit, the test word is connected to the fifth output of the control unit. 2. The device according to claim 1, wherein the control unit comprises three AND elements, an OR element, a delay element and a decoder, the group of information inputs of which is a group of block address inputs, first, second, third, fourth and n which paths are connected to the outputs of the first element AND, the second element AND, the delay element, the third element AND and the OR element, respectively, the strobing input of the HEI control unit with the first inputs of the first, second and third elements AND, the second input of the first element And connected to Q is the first output of the decoder, the second output of which is connected to the second input of the second element AND and the first input of the element OR, the second input of which is. That is combined with the third entrance of the third  element and and connected to the third the output of the decoder, the recording input of which is the input of the recording resolution of the control unit, the output of the first element I, is connected to the input of the delay element, 3. The device according to claim 1, wherein the block forming the test word contains gei; clock nepator, two counters, element I, element IL.I5 two shift registers and a switch, the group of information inputs of the first shift register is a group of information inputs of the block, the group of information inputs of the mask of which is connected to the group of information inputs of the switch, the group of control the inputs of which are connected to the group of outputs of the bits of the first counter, the overflow output of which is connected to the first input of the OR element and is the readiness output of the block test word, the readiness output parts of the test word of which is connected to the output of the OR element and the input of the first shift register, the input of which is connected to the clock input of the second counter and connected to the element AND whose first input is connected to the output of the clock generator, the clock input of the first counter and the second shift input the shift register, the blocking input of which is combined with the blocking inputs of the first and second counters II, is the block start input, the mode setting input of which is connected to the control input of the switch, the output which is connected to the second entrance 5: And, the serial output of the first shift register is connected to the serial input of the second shift register, a group of WAYS which0 five 0 714116 UZ8 Pogo is a group of informational second counter connected to the second output of the block, the output of the overflow input of the OR element.