SU1432530A1 - Apparatus for monitoring logical modules - Google Patents

Abstract

The invention relates to the field of computer technology, in particular, to means of automated control of digital objects, and can be used to test digital circuits built using structural design methods. The purpose of the invention is to increase the reliability of control by allowing the automated generation of a given test sequence at an arbitrary point in the circuit. The device consists of a counter, a monitored digital block, a first and second memory blocks, a microprogram control unit, an information register, multiplexers, shift registers, the first, second, third switches, the first and second address counters, the fourth switch, the element group And, the element group OR, from the buffer register, the first and second triggers, the AND element and the comparison circuit. The use of microprogram memory in the control unit allows to significantly increase the efficiency and informativeness of the control results. 3 il. Sfi (L S

Description

one

The invention relates to a variety of engineering techniques, in particular, to means of automated control of digital objects, and can be used to test digital circuits constructed using structural design methods.

The purpose of the invention is to increase the reliability of the control.

FIG. 1 is a block diagram of the device; in fig. 2 is a functional diagram of the control unit j in FIG. 3; a functional diagram of the comparison

The device (Fig. 1) contains a counter 1, a controlled digital block 2, a memory block 3, a microprogram control unit 4, a switch 5, a mask register 6, K multiplexers 7, K shift registers 8, switch 9, switch 10, the first AND.address counter, memory block 12, switchboard 13, address counter 14, AND group, 15 OR group, buffer register 17, And 18 element,. triggers 19 and 20, comparison circuit 21

The device works in the following way.

Depending on the structure of unit 2, the required mode of operation of the test driver may be selected. Consider, for example, testing a circuit implemented using structural methods of checkable design. The essence of the control of such a device is the separate testing of combinational and sequential parts. The mode of creating a given test sequence

.12) With the help of counter 1, code combinations are looped through the inputs

in arbitrary combinator-40 multiplexers 7. The sequence part of the circuit is enlarged by the following algorithm.

characters from the output of an arbitrary multiplexer is rewritten into block 3. 13) Instead of a reference product, a digital is connected to the device

1) In block 3 from an external medium, a binary sequence of symbols from the output of an arbitrary multiplexer is recorded in block 3. 13) Instead of a reference product, a digital is connected to the device

In this case, in which logical 1 in 45 block 2 and the counting function, only the memory cell with an address multiple of a power of two is converted.

2) From block 3, the information is rewritten into one of the registers 8.

3) The procedure described in the first and second steps is repeated as many times as the digital block 2 has inputs. It is necessary that the single bit of information is present each time in a new memory cell whose address is a multiple of a power of two.

4) The counting functions generated by counter 1 are fed through multiplexers 7 to the inputs of switch 5 and che50.

55

Multiplexers 7 through the switch 5, group 15, group 16, register 17, are fed to the inputs of the monitored digital unit 2.

14) The reaction of the monitored digital block 2 at a given point at each clock cycle through the switch 13 records in block 12.

15) Block 3 and block 12 are read and the read information in diagram 21 is compared. Illumination of the indicator at the end of the comparison indicates improper function.

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rez elements OR group 16 and register

17 is applied to the inputs of block 2. A sequence of signals taken at each time step is recorded in block 12.

5) The control reaction is rewritten from block 12 to one of the registers &

6) With the help of counter 1, the code combinations are searched at the inputs of the multiplexers 7. The sequence of symbols from the output of the multiplexer, as defined (described in step 5, through the switch 5 is recorded in block 12.

7) The test sequence, which must be formed at the above point of block 2, is entered through switch 10 into block 3.

8) The information from block 3 is overwritten to one of the registers 8.

9) With the help of counter 1, the code combinations are searched at the inputs of multiplexers 7. The sequence of symbols from the output of multiplexer 7, defined in step 8, through the switch 5 is recorded in block 3.

10) The information from block 3 is copied to all reg ister 8.

11) Block 12 is put into read mode, and trigger 20 is set to one. When the first unit bit is counted from block 12, trigger 19 generates a control signal for block 4, which causes the counter 14 to stop and its contents to be written to register 6.

.12) With the help of counter 1, code combinations are looped through the inputs

20

25

thirty

35

40 multiplexers 7. Sequence multiplexers 7. Sequence

characters from the output of an arbitrary multiplexer is rewritten into block 3. 13) Instead of a reference product, a digital is connected to the device

block 2 and counting functions, converted0

five

Multiplexers 7 through the switch 5, group 15, group 16, register 17, are fed to the inputs of the monitored digital unit 2.

14) The reaction of the monitored digital block 2 at a given point at each clock cycle through the switch 13 records in block 12.

15) Block 3 and block 12 are read and the read information in diagram 21 is compared. The glow of the indicator at the end of the comparison indicates improper function.

the checked circuit at the selected point. The absence of light indicates the health of the controlled unit.

To form the required test sequences at the circuit inputs, you must perform the following steps.

In block 3 from external carriers, the test sequence is a test sequence which must be formed at the i-M input of the monitored block.

From block 3, the information is copied to the i-th register 8.

The counting functions generated by counter 1 are fed to the inputs of multiplexers 7. A sequence of symbols from the output of the i-ro multiplexer 7 through the switch 5 is recorded in block 3.

The information from block 3 is rewritten into i-th register 8.

Further, this algorithm is repeated until all registers 8 are filled with the relevant information. Then the test mode is activated. At the same time, the counting functions of counter 1, converted by multiplexers 7, are fed to the inputs of the switch 5, and then through group 16 and register 17 to the inputs of block 2.

Claims (1)

Invention Formula A device for controlling digital blocks comprising a counter, a first memory block, a microprogram control unit, a mask register, the counter count input and the mask register synchronizing input are connected to the first and second outputs of the first sync | microprogram control block, characterized in that in order to increase the reliability of the control, K has been entered into it. multiplexers, where K is the number of inputs of the monitored digital block, K shift registers, four switches, the first and second address counters, the second memory block, the group of elements AND, the group of elements OR, the buffer register, the first and second triggers, the element And and the comparison circuit , the bit outputs of the counter are connected to the group of control inputs of the i-ro multiplexer (, K), the outputs of the multiplexer of the group are connected to the information inputs of the first switch, the group of bit outputs of the K register 0 five The shift pins are connected to the group of information inputs of the corresponding M1GX multiplexers of the group, the information inputs K of the shift registers are connected to the outputs of the second switch, the first and second groups of information inputs of which are connected to the group of outputs of the first and second memory blocks, respectively, and the first and second groups information inputs of the comparison circuit, the address inputs of the first and second memory blocks are connected to the bit outputs of the first and second counters of the address cooTtffeTCTBeHHo, the information input and the input of the record and the second memory unit are connected to the first and second outputs of the third switch, respectively, the information input and the recording input of the first memory block are connected to the first and second outputs of the fourth switch, respectively, the third output of which is connected to the counting input of the first address counter, the first group of outputs of the first switch -. is connected to the first inputs of the elements of the OR group, the second group of outputs of the first switch is connected to 0 first inputs of the AND elements of the group, the second inputs of which are connected to the corresponding outputs of the mask register, outputs of the AND elements of the group are connected to the second inputs of the elements of OR groups whose outputs are connected to information the inputs of the buffer register, the outputs of which are the outputs of the device for connection to the inputs of the monitored digital block, the bit outputs of the second address counter are connected to the information the mask register, the output of the first switch is connected to the first information inputs of the third and fourth switches; the input of the element And is connected to the output of the second memory block, the second input of the element And is connected to the output of the second trigger, the output of the element And is connected to the input of the installation the first trigger, the sync inputs To the shift registers, the control inputs of the first, second, third five 0 five 0 five na Phage. 2 CUSH managers. From block-GP From ylok CHA J From olona19- From 6 / fOf (ct 1 - | Bp From SJIOKU S 9m SjtoKu / 2 a l-tshp 52 From block Phi1.3