SU1267425A1 - Microprogram device for generating test sequence - Google Patents

Abstract

This invention relates to an ultrasonic technique. The aim of the invention is to increase the utilization of equipment. The invention contains a memory block, address registers, states, frequencies, returns, output registers, masks, a control unit, a counter, a comparator, a multiplexer, key blocks, a group of elements I. The device automatically generates test sequences for various types of modules to be tested. . 1 hp f-ly, 25 ill. (L

Description

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The invention relates to computing technology, in particular to a device for automatically synthesizing tests for health monitoring and diagnostics of complex digital objects,

The aim of the invention is to increase the utilization ratio of the equipment.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 is a functional block diagram of the control unit; in fig. 3 - generator circuit; in fig. A - diagram of the synchronization node; in fig. 5 is a pulse shaper circuit; in fig. 6 diagram of the switch launch conditions; in fig. 7 is an address switch circuit; in fig. 8 is a diagram of the first decoder; in fig. 9 is a diagram of a control signal switch; Fig.10 is a diagram of the second decoder; figure 11 diagram of the node delay; in fig. 12 switch layout; in fig. 13 is a switch circuit; in FIG. 14 is a diagram of the second and third units; in fig. 15, 16 - block diagrams before. setting the initial conditions; in fig. 17 —the format of the address register, frequency register, and status register; in fig. 18 — memory block format; in fig. 19 - formats 0,1,2; in fig. 20 - encoding of the words of the memory block in the formats O ,, 1,2; Fig. 21- is the decoding of memory words by microoperations in formats O, 1.2; in fig. 22 is a temporary diagram of the operation of the address register; in fig. 23 is a time diagram of the operation of the decoder; in fig. 24 is a timing diagram of a test sequence generating mode; in fig. 25 is a temporary diagram of the preliminary preparation (loading) mode.

The prearranged device (Fig. 1) contains a memory block 1, an address register 2, a status register 3, a frequency register 4, a return register 5, an output register 6, a mask register 7, a counter 8, a digital comparator 9, a multiplexer 10, the first block 11 keys, an AND group 12, a second key block 13, a third key block 14, a control block 15, a preset block 16, an output information bus 17, an input control bus 18, an input information bus 19, an output control bus 20,

The control unit (Fig. 2) contains a generator 21, a pulse shaper 22, a synchronization node 23, a com-mutator 24 trigger conditions, the first

a decoder 25, a cochmutator of control signals 26, an address switch 27, a mode switch 28, a delay node 29, a switch 30, a second decoder 31, block codes 32-43

management,

The generator 21 (FIG. 3) contains a block 59, including 1st inverters 44-45, resistors 50 and 5, a capacitor 52, a quartz resonator 53. In addition, the generator contains inverters 46-49.D-triggers 54 and 55, an element AND NOT 56, outputs 57.58 of the generator.

The synchronization node (figure 4) contains a binary counter 60, two multiplexers One of N 61.62 and inverter 63.

The shaper smpulsov (figure 5) contains the element And 64, triggers 65

and 66.

The switch trigger conditions (Fig.6) contains inverters 67 and 68, elements AND-NOT 69-71, and 72, two D-flip-flops 73 and 74, elements And 75.76.

The address switch (Fig.7) contains the elements AND-NOT 77-79, the elements And 80,81, inverters 83 and 84.

The first decoder (FIG. 8) contains an AND-NE element 85-91, and 92-95,

IPI-HE 96, inverters 97-100, decoder 101, Vykoda 102-109 of the first decoder.

The switchboard of control signals (FIG. 9) contains elements of NAND

110-118, inverters 119 and 120, elements AND 12-1-123, control switch outputs 124-129.

The second decoder (figure 10) consists of D-flip-flops 130-135, elements

And NOT 136-140, the inverter 141, the element 142 delay.

The delay node (11) contains the D-trigger 143, the elements AND-NOT 144-146, the element And 147, the inverter 148.

The switch (FIG. 12) contains AND-HE elements 149, and 150.

The switch (FIG. 13) contains two D-flip-flops 151., 152 and AND-NOT elements 153, 154.

Claims (2)

The second and third blocks of the keys (Fig.14) contain two blocks of two-way amplifiers 155,156. 3 A pre-installation block of initial conditions (Fig.15, 16) contains a series of information toggle switches 157-161, a series of keys 162-166, an AND-NE element 167, a series of LEDs 168-172, a number of resistances G73-177, a series of toggle controls 178-184, a control button 185, outputs 186,187 of a presetting unit for initial conditions. The device works as follows. The firmware for the formation of the test sequence (Fig. 1) has two main modes of operation; preloading into registers and the initial information memory (Fig. 25); generating a test sequence (Fig. 24). . . In the mode of preloading into registers and the memory of initial information, the device can be in the Stop state, and in the mode of generating the test sequence, first in the Pre-start state, then Start. The Pre-Start condition may be missing. If there is an O signal on line 35 of the Operating Mode (Fig. 16), the device is in the Stop state. In this state, the write and read modes are provided, the time diagrams of which are shown in Fig. 25. Information is stored in the address register 2, the status register 3, and the frequency register 4 (Fig. 1) according to the algorithm shown in Fig. 25. The information is set by the values of the signals at the outputs of the presetting unit 16 (Fig. 15), which is fed to the group of inputs and outputs of the second key unit 13. Signal About toggle switch ZPRS, RF, RA in blo. The preset ke 16 (Fig. 16) is supplied to the control unit 15, whereby the gates are written to the address, state and frequency registers 2-4, respectively (Fig. 1). Memory unit 1 is a storage unit with a capacity of, for example, 1024 to X 34 bit words, and the read from preset unit 16 is performed block by block by sixteen PAMO bits, PAM1} PAM2 (Fig. 18). The identification of the memory block is carried out by applying to one of the control lines of the FPA, the CWP, the FOD2 (Fig. 16) of the signal O. When the register address state 2 changes to 25, the information is addressed to another cell of the memory 1. Writing the low-order state register 3 to a value of 0 or 1 (Fig. 17) determines the starting condition of the device. The transition of the device from the Stop state to the Start state is carried out in two ways, depending on the value of the low-order bits of the state 3 register (Fig. 17). If the value is 1, the device is allowed to enter the Start state by a signal on line 35 of operation (FIG. 1), and if the value is O by an external signal on line 18 (FIG. 1). The device has the third state Pre-start, which is defined as an intermediate state between Stop and Start. In this state, the device will be after the signal on the line 35 has switched from the value O to 1 (in the 3 register, the discharge state determining the trigger condition is O), and the external trigger signal on the line 18 from the diagnostic object is not yet on the forks. The transition of the device to the Start state means the transition to the test sequence generation mode (execution of the test diagnostic program recorded in memory block 1). It is carried out in two re-. presses - automatic and step by step. In the automatic mode, the execution of commands is performed without operator intervention by a program that is previously stored in memory block 1. In stepping mode, a constant initiation from the operator's string is required to execute each command. The execution of the next command of the device is initiated by reading the PAM2 block (Fig. 18). The generation of the test sequence in the Step or Auto mode is determined by a 34-bit block. memory PAM2 (Fig.18). In the test sequence generation mode, a word is selected from memory block 1 whose address corresponds to the value of register 2 of the address (Figure 1). The three most significant bits of this word define the format of the command. The device has three command formats (Fig. 19). in the format O, the following device commands are provided: write half-dynes (FIG. 20) to the output register 6; writing the data field (FIG. 20) to the mask register 7; waiting for events in which the control unit 15 (figure 2) generates signals that fix memory 1 on the selected word, start the counter 8, the fourth input of which is supplied with the clock signals from the control unit 15 (figure 1), and the fifth signal resolving a level 1 count from the same block. Register 2 addresses are waiting for one of. two events: comparing the contents of the data field (bits DAM 31 ,,. 00) with the values of the signals on the input channels 19 device (Fig. 20) taking into account the masking times 7 of the mask in accordance with the rows in the VII register with the expression F: X- (to 3, .. 00 5rPtl 31 ... .. where K is the kth input channel of devices. R is a data field, bits are PA11 31 .... overflow of counter 8, which is started by micro-operation Waiting for events, At the first event the value of register 2 addresses (PA) is increased by two (PA: RA + 2), at the second event the value of PA is increased to one (PA: RA + 1). After tracking Ani of one of the two indicated events realized with the O format (micro wait operation), the device proceeds to parse the next command selected from the memory block. On the Record full dan to the output register command, the selected word is written., 00 to the register 6 output , and a unit (PA: PA + 1) is added to address register 2, and the following word is selected from memory block 1. On the Record data field command to the mask register (SPRM), the CAM 31 ... 00 word is written to register 7 masks, and one is added to the RA and the next word is selected from In memory 1, format 1 (FIG. 21), the following commands are executed: write the data field to the address register 2, write the data field to the return register 5. After executing any of the commands, the value of the PA 2 register is increased by one (PA: PA + 1), the next word is selected from memory block 1. 25 In format 2 (FIG. 21), the following commands are issued: issuing a radial stop request 38 (FIG. 2) to the diagnostic object, transmitting the return register value 5 to the address register 2, writing the data field to the counter 8, and opening the radial stop request 38 ( 2) and stop the device. In this format 2, combinations of the above commands are possible under the condition that the recordings of the frequency register data field and the counter data field should not be performed when the code entered in the frequency register matches (or is not significant for this state of the frequency register) with recorded in the three least significant bits of counter 8 (see overlapping fields 2 and 3 of FIG. 20). The radial request signal 38 of the device (FIG. 2) is generated when the device is operating in the sequence generation mode and executes format 2 commands in two cases: when performing the operation of issuing the radial request 38 for stopping the diagnostics object and stopping the device, GSHI 30 0; when executing a command to issue a radial request 38 for stopping the diagnostics object IIAM 1 26 0. Claim 1. Microprogramming device for generating a test sequence containing a memory block, an address register whose outputs are connected to the address input of the memory block, an output register, a group of elements And, The first inputs of which are connected to the outputs of the object to be diagnosed, a presetting unit, a counter and a control unit, characterized in that, in order to increase the utilization rate of the equipment, it contains a mask register, a return register, a frequency register, a status register, three key blocks, a digital comparator, a multiplexer, the address group of the outputs of the memory block is connected to the first data inputs of the output register, mask register, digital comparator, multigatexor, with information inputs address register, with the address group of outputs of the second key block and outputs of the return register, the group of outputs of the code of the memory block frequency code is connected to the second data inputs of the output register, mask register, multiplex a digital comparator, with the first data inputs of the counter, return register, frequency register, with the frequency output group of the second key block, the output group of the return code of the memory block is connected to the third data inputs of the output register, mask register, digital comparator, multiplexer, with the second data inputs of the register of the counter return, the group of outputs of the code for the meter is connected to the fourth data inputs of the output register, mask register, digital comparator, multiplexer and the third input With the data of the counter, the group of outputs of the code of the code of the memory block commands is connected to the fifth data inputs of the output register, the mask register, digital comparator, multiplexer, the inputs of the code of the code of the control block, the group of outputs of the sign of the format of the memory block commands is connected to the inputs of the sign the command format of the control unit, with sixth multiplexer data inputs, the address group of inputs of which is connected to the control output group of the control unit multiplexer, the second group of control outputs of the control unit The output unit is connected to the group of control inputs of the third key block, the group of information inputs of which is connected to the multiplexer output group, the output of the state indication of the control unit is connected to the status input of the second key block, the information group of the outputs is connected to the information inputs of the register No, the clocking input of which is connected to the output of the sign of writing to the state register of the control unit, the group of outputs of the sign of writing to the address of which is connected to The clocking inputs of the address register, the output group of which is connected to the address input group of the second unit, the input group of the frequency code of which is connected to the control input group of the same name and to the output register group of the frequency register, the clocking input of which is connected to the output register of the control unit , the installation group of inputs of which is connected to the information group of inputs of the memory block and with the group of outputs of the third key block, the group of inputs-outputs Address-data of which is connected not with input-output group Address-data of the second key block, with input-output group Address-data of the preset unit, the interface output group of which is connected to the interface group of control unit inputs, the overflow sign input of which is connected to the counter overflow output, the clock input of which is connected to the output of the write attribute to the counter of the control unit, the output of the write characteristic to the mask register of the control unit is connected to the clock input of the mask register, the output group of which is connected to the second inputs of elements AND groups, the outputs of which are connected to the sixth group of data inputs of the digital comparator, the output of the comparison attribute of which is connected to the input of the comparison indicator of the control unit, the output of the counting resolution of which is connected to the control input of the digital mapator, and the output of the sign of issuing information of the control unit is connected to the input of the permission to issue information of the first key block, whose information inputs are connected to the outputs of the output register, and the output to the outputs The device clocking the output register is connected to the output of the write to the output register of the control unit, the group of outputs of the write to the return register of which is connected to the group of clock inputs of the return register, the outputs of the state register are connected to the information group of inputs of the control unit and the information group of inputs the second key block, the group of outputs of the control unit of the memory unit of the control unit is connected to the group of inputs of the chip sample and the write-read of the memory unit, the group of outputs with rovozhdeni information control unit connected to the control device outputs yushd E, and start the control unit input is connected to a control input device. 2. A device according to claim 1, characterized in that, the block; control contains generator, pulse shaper, start condition conditioner, synchronization node, first decoder, address switch, mode switch, delay node, switch, second decoder, control signal switch, with the first input of the first decoder connected to the first control input an address switch and with the first control output of the second decoder, the first control input of which is connected to the first control output of the first decoder, the second information input of which is connected to the second The information output of the second decoder, the second clock input of which is connected, to the first clock output of the synchronization node, the second control output of which is connected to the third control input of the second decoder, the fourth clock input of which is connected to the first clock input of the delay node and the third the clock output of the synchronization node, the first input of which is connected to the first output of the generator, the second output of which is co-ordinated with the first control input of the control switch commutator, the second the information input of which is connected to the first information output of the mode switch, the first control input of which is connected to the first information output of the control switch, the third information input of which is connected to the second input of the mode switch and the first output of the delay node, the second information output the input of which is connected to the second information output of the first decoder, the third information output of which is connected to the third input of the delay node, the fourth information input of which It is connected to the first information input of the switch of launch conditions and to the information output of the switch, the first control input of which is connected to the second control input of the switch of start conditions and to the fourth output of the first decoder, the fifth output of which is connected to the third information input of the address switch, The second control input of which is connected to the second output of the delay node, the fifth input of which is the input of the overflow sign of the control unit, the third output of the delay node is the output recognized Record in the control unit counter, the third output of the second decoder is connected to the second information input of the switch and to the fourth information input of the control switch, the fifth information input of which is connected to the fourth information input of the address switch and to the sixth output of the first decoder, the seventh output of which is The output of the write attribute to the frequency register of the control unit, the second input of the synchronization node is the input of the frequency code of the control unit, the third input of the synchronization node Connected to the first output of the pulse generator, the second output of which is connected to the third control input of the start condition switch, the fourth control input of which is connected to the sixth control input of the control switch, and the first input of the pulse generator and the interface input of the control unit, the third the generator output is connected to the fourth input of the synchronization unit; the fourth generator output is connected to the second input of the pulse generator, the third input of which is connected to the first information the switch output ion output, the second and third information outputs of which are connected to the third and fourth inputs of the mode switch, respectively, the second output of which is connected to the fifth input of the second decoder, the fourth output of which is connected to the fifth information input of the address switch, first and second information outputs which are the output of the sign write to the address register of the control unit, the eighth and ninth outputs of the first decoder are the outputs of the tracking information of the device tva, the tenth output is the output of the write to the reset register, the one-tenth output is the output of the write to the mask register, the twelfth output is the output of the write to the output register, the second output of the control switch is the output of the device’s memory block , the sixth input of the delay node is the input of the control unit comparison feature; the fourth output of the delay node is the output of the resolution I of the control unit; the fifth input of the mode switch is connected to the fifth output of The decoder, the sixth output of which is connected to the sixth input of the address switch, the seventh input of which is connected to the third input of the first decoder, is connected to the third output of the control switchboard of the control signals and is the output of a sign into the state register of the control unit, the fifth input of the switch trigger conditions are the information input of the control unit; the third output of the mode switch is the control output of the control unit multiplex; the fourth and 2512 fifth inputs of the first decoder are inputs recognized As the code and command format of the control unit, the sixth input of the condition switch starts up the start input of the control unit, the sixth input of the mode switch is the setup input of the control unit, the third output of the output group of the preset block is connected to the third input of the gating unit, the seventh input of the mode switch is the interface input of the control unit; the fourth output of the control signal switchboard contains the outputs for indicating the status and indication of the output of the information of the control unit, the fifth high The control signal switch stroke is connected to the third input of the switch. FIG. one go5i g 2 "I-" TL-j "L " 55 Phage. four Faye. b CPus.6 Omff / r. 31 TT OmSfi.25 Lg OmSff.26 32 ffff.2 Jj 79 0 / nS / T.2S From 5l. 31 FIG. 7Sh109 OmSa.l eel t OPI .GZ FIG. eight ffMO, ff, fJ  3.15,27 / Cffjf.29 FIG, il FIG. 12 Thebes. 13 Ot5l.16 From IL. i6 Fi8. f6 RFPA PC FIG. 17 PAMO PAM1 FIG. f8 eleven 1 X o / - 1 oo - Format 2 32x51 30 h / V Paleo Microoperations (uMOcpfiaaua) Fo / ZmaO  ... iguhod 00 Formata Micro-operation Psh, ed1 Psh edannsh2 nAM 3j2jn JO ... 26 25..f2 // ... OO Format 2 Microopdraction Field 2 Goz fToflef About format Fi2.19 0100 FIG. 20 i1 1О О1 ОО 01 1О I1 II 11 11 10 01 a) Records 9 petucmp addresses of daddies 2 psgolleelny information J Managed simal  CmpoS Records Format O-throwing (OJ) -sanuctf words b Pesttcmp bc (input-saling words to the Register Format 1 RA: field Of РВ- pole1 RA oleo O absence of operation Format 2 11О Issuing radial eo sofyjoco 1О1 РА-.РВ 011 pi /: "/ to / re.J 111 RT: / Yule2 111 Btfdava fladuaMMfff Fayo.21 38 to the diagnostic object b8 and ocmof e S) -t-lS register /} memory address g (countable pe / ttu /) 144 144 - (Mres (data th lzp 773 FIG. 24 BUT five -- Address Xx / MBP / ADHT X OGV 5} Cycle tne $ FIG. 25