SU964618A1 - Information input device - Google Patents

Description

(5) DEVICE FOR ENTERING INFORMATION

one

The device relates to automation and can be used in the construction of input devices.

A device for inputting information is known in which the switching elements are polled with a scanner via a decoder. When switching on the switching element, an encoder executed on logic circuits generates an IQ code of the group and stops the counter, at the output of which the code SPN is installed. logic circuits, the counter and the decoder is a torus form a very complex circuit.

The closest to the invention in terms of the function performed and the result achieved is an information input device, in which from the pulse generator through the open element | Ment And the pulses are fed to the input of the counter, from the output of which the binary

The CODE is converted to decimal dyuf rattor, and the tayuha is sent to address-. switch inputs. The decoder polls the switching elements of the matrix on the vertical bus, horizontal bus connected to the input of the switch. When the switching element is turned on, the switch generates a pulse that flips the trigger to another state, prohibiting the passage of pulses from the generator through the element AND to the counter input. At the output of the counter, the code of the corresponding switching element is established. When the switching element is switched off, the trigger is reset to its initial state through a delay element that delays the si-nal for the time of bounce in the switching element 2 ..

Claims (2)

The known device has the following disadvantages. Code generation is carried out in a sequential scheme in three stages, when the binary code from the counter output is converted into a decryptor (step), then the decimal code is converted into a serial code by the switch (stage 2), the generated signal is stored by a trigger (stage 3) and issued to the device output. Such transformations, when forming a code, increase hardware costs. At the output of the device, code combinations are formed regardless of whether the switching element is on or not. The trigger, having triggered, generates a signal indicating that at the output of the device the code corresponds to the switched on switching element. Therefore, it is necessary to gate the outputs of the counter with a signal from the trigger, namely to introduce the elements I, which leads to an increase in hardware costs. The device has a rigid structure, since it forms only one specific code for the exchange of information and. To form another type of exchange code, for example, ISO, KOIKOI-8, etc., it is necessary to increase the device, which increases hardware costs and reduces the functional capabilities of the device. The aim of the invention is to simplify the device. This goal is achieved by the fact that in a device for inputting information, containing an array of switching elements with output buses and with the first and second groups of input buses, a pulse generator, the output of which is connected to the first input of the AND element, the trigger whose output is the first output of the device, the first and second memory blocks shift register and the OR element, the output of which is connected, with the second input of the AND element and with the first inputs of the first and second memory blocks, the second inputs of which are connected and are the input of the device Twa, the third input of the first memory block coupled to inputs of the OR gate and output lines of the matrix of switching elements, input buses of the first and second groups are connected to the tre tim and fourth inputs of the second blo ka memory whose output is; the second output of the device, the output of the first memory block is the third output, the device, the first input of the shift register is connected to (And output 84 of the And element, the outputs of the shift register are connected to the input buses of the first and second groups of the matrix of switching elements, the first bus of the first group of input bus connected to the trigger input, the second input of which is connected to the first bus of the second group of input tires. The drawing shows a structural; device for entering information. The device contains a pulse generator 1, the element And 2, shifting register 3 matrix of switching elements, element OR 5, first memory block 6, second memory block 7, and trigger 8. The device operates as follows .pai3OM.. Clock pulses from the output of an Iropa 1 pulse arrive at one input of the AND element 2, to the other input of which the permitting signal is transmitted from the element OR 5 when the switching elements of the matrix are in the initial state (not pressed). When switching on the switching element of the matrix, the inhibiting signal from the generator 1 is transmitted from the element OR 5 in chepez ele ent and 2. receipt enable signal to the other input of AND 2 pulses supplied from the pulse generator 1 through the AND gate 2 to the input of shift register 3 is shifted recorded in the initial state, the logical unit register. At the exit of the shift register 3 clock pulses interrogate the switching elements of the matrix on vertical tires. When the switching element of the matrix l is turned on, the signal from the corresponding output of the shift register 3 through the vertical bus of the matrix k and the closed contact of the switching element goes to the horizontal bus of the matrix 4, while vertical, the address of the higher bits indicates the bus, and the horizontal bus is the address of the lower bits Dov. From the horizontal bus, the address of the least significant bits is supplied to the address input of the first memory block 6, which generates the code of the lower bits, and from the vertical bus, the address of the higher bits goes to the address input of the second memory block 7, which generates the higher-order code, moreover, at the output of the device, in the vehicle code combinations only when the address of the choice of the code for the exchange of information from an external device, carrying information about the lower and senior bits of the code and authorizing the data sampling signal from the first memory block 6 and the second memory block 7. When an OR 5 element is triggered (the switching element of the matrix k is on), the pulse is not allowed to pass into the shift register 3 and the signal from the OR 5 element is simultaneously the enabling signal, which is fed in parallel to the sample enable input of the first memory block 6 and the second block 7, the low-order code code rows of the first memory block 6 and the high-order bits of the second memory block are read out. From the first vertical bus of alphanumeric switching elements of the matrix k, the signal flips trigger 8 to one state, and the signal from the first bus of the functional switching elements of matrix 4 returns trigger 8 to its initial state. At the same time, the output of logic 1 from trigger 8 indicates that the formed code at the output of the device corresponds to the character code, and logical O corresponds to the command code. Selecting the frequency of the pulse generator eliminates the device's susceptibility to contact jingling, which made it possible not to introduce a delay element. The device has a flexible structure, as for the formation of various information exchange codes from an external device, an address for selecting the information exchange code is output to the address inputs of the first memory block and the second memory memory generating different information exchange code, which expands the functionality of the device. Apparatus for inputting information, comprising an array of switching elements with output buses and with the first and second groups of input buses, a pulse generator, the output of which is connected to the first input of the element I, a trigger, the output of which is the first output of the device, characterized in that In order to simplify the device, the first and second memory blocks are entered into it, shifting the register and the OR element, whose output is connected to the second input of the AND element and to the first inputs of the first and second memory blocks, the second inputs which are connected and are the input of the device, the third input of the first memory block is connected to the inputs of the OR element and to the output buses of the matrix of switching elements, the input buses of the first and second riiynn of which are connected to the third and fourth inputs of the second memory block, the output of which is the second the output of the device, the output of the first memory block is the third output of the device, the first input of the shift register is connected to the output of the AND element, the outputs of the shift register are connected to the input buses of the first and second matrix groups ommutatsionnyh elements, the first group of the first bus input lines connected to the first input of the flip-flop, a second input coupled to a first bus input lines of the second group. Sources of information taken into account in the examination 1. USSR author's certificate number 995b5, cl. G About F 3/02, 197t. 2. USSR author's certificate number 669350, cl. G About F 3/02, 1978 (prototype) ... A / FoSe // 77 // ffg / g / 0 I - / - ..I y / rgfi / ff ff AMXf | .. T A / fff /