SU1585790A1 - Device for information input - Google Patents

Abstract

The invention relates to automation and computing and can be used to enter information from a keyboard in various digital devices and devices. The device provides a higher speed by reducing the time to form the code of the closed switching element and the time to form the positive (negative) front of the strobe signal relative to the closing time of the switching element. The interrogation of the matrix 4 of switching elements in the device is carried out in whole rows and columns. During each pulse period, the pulse generator 1 (for each state of counter 2) checks for the presence of a closed switching element in the 1st column and the 1st row of matrix 4. During the first half period, all horizontal buses of matrix 4 are received LOG "1" from the key group 14 and the output of the multiplexer 5 connects the I-vertical bus of the matrix 4. If the I-th vertical bus has a closed switching element, then the LOG signal "1" appears at the output of the multiplexer 5, the trigger 9 is activated and R Trunk code number 11 is recorded vertical bus on which the switching element is closed. Similarly, in the second half-cycle, all vertical busses of matrix 4 receive LOG signals "1" from key group 13 and I-horizontal bus of matrix 4 is connected to the output of multiplexer 3. If there is a closed switching element on the I-th horizontal bus, then the output of multiplexer 3 the LOG signal "1" appears, trigger 6 is activated and in the register 12 it writes the code of the horizontal bus number. Trigger 10 triggers and, accordingly, the output of the gate signal device occurs by a positive signal drop from the inverse output of the high bit of counter 2 after both triggers 9 and 6, i.e. when codes of numbers of vertical and horizontal buses, at the intersection of which there is a closed switching element, are determined and recorded in register 11 and 12. 4 il.

Description

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oo ate

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telny) the front of the strobe signal relative to the moment of closing (opening) of the switching element. The interrogation of the matrix 4 of switching elements in the device is carried out in whole rows and columns. During each period of the following impuhs from the pulse generator 1 (for each state of counter 2), r is checked (checking for the presence of a closed switching element in the i-th column and the i-th row of the matrix 4. During the first half period horizontally, similarly, in the second half period, all vertical busses of matrix 4 receive signals from log 1 from key group 13 and i-horizontal bus of matrix 4 is connected to the output of multiplexer 3. If there is a closed switching element on the i-th horizontal bus, then out At multiplexer 3, a siggal of log 1 appears, trigger 6 triggers, and a horizontal bus number is written to register 12. Trigger trigger 10 and respectively

Tap tires Matrix 4 arrive at the level at the device output of the gating, 1 from the group of keys 14 and

not a log,

the output of the multiplexer 5 connects the i-vertical bus..matrix 4. If there is a closed switching element on the i-th vertical bus, then 20 at the output of multiplexer 5 a log signal appears, 1, the trigger 9 is triggered and the vertical bus number is written to the register 11 on which is a closed switching 25

signal occurs on the positive differential signal from the inverse output of the higher bit of counter 2 after both triggers 9 and 6, i.e. when codes of numbers of vertical and horizontal buses, at the intersection of which there is a closed switching element, 4 slug are determined and recorded in register 11 and 12.

The invention relates to automation and computing and can be used to enter information from the keyboard in various digital devices and devices.

The aim of the invention is to improve the speed of the device.

FIG. 1 shows a functional diagram of the device; in fig. 2-4 - timing charts, on. Sun Yush; and his work.

The device contains a generator 1 pulses 5 counter 2, the second multiplexer 3, the matrix 4 switching elements, the first multiplexer 5, the third trigger 6, the element NOT 7, the element And 8, the first 9 and second 10 triggers, the first 11 and the second 12 registers the first 13 and The second 14 groups of keys and resistors 15.

The device works as follows.

When the power source is turned on, a device pulse is applied to the reset input of the device, setting triggers 6, 9, and 10 and registers 11 and 12 to their initial state. Thus, up to the first closure of the switching element in the matrix 4, the information

the output of the gating device

signal occurs on the positive differential signal from the inverse output of the higher bit of counter 2 after both triggers 9 and 6, i.e. when codes of numbers of vertical and horizontal buses, at the intersection of which there is a closed switching element, 4 slug are determined and recorded in register 11 and 12.

five

0

five

0

five

and the strobes of the devices are in the zero state.

For each negative differential at the output of the pulse generator 1 (Fig. 2), the state of the counter 2 is switched (in Fig. 2, B-i shows the change in the state of the lower bit of the counter 2). The code combination taken from the outputs of the counter 2 group controls the operation of multiplexers 3 and 5. The multiplexer 5 operates in such a way that if its control input has a logic zero level, then depending on the binary code coming from the counter 2 group output to its address inputs, a signal (logical 1 or logical O) is switched from one of the information inputs of the multiplexer to its output. If logical level 1 is present at the control input of the multiplexer, then the multiplexer operation in this case is prohibited and its output is in the third (disabled) state. Multiplexer 3 works in the same way.

Consider the operation of the device with open contacts in the matrix 4 in

during one period of the following pulses from generator 1 (for example, in the time interval t, - t., in figure 2), considering that in subsequent periods the operation of the device (with open contacts of the matrix 4) occurs in a similar way.

Over time t

, - t (the first half period) signal of logical 1 from the output of the element NOT 7 (Fig. 25), inverse with respect to the signal from the output of the pulse generator 1 (Fig. 2a), is fed to the control inputs of the second group 14 of keys, with the result all keys 14 of the group are in the closed state and at their outputs there are logical 1 levels (supply voltage E). These signals of logical 1 are received simultaneously to all horizontal busbars of the matrix 4 switching elements and, accordingly, to all inputs of the multiplexer. Since during the time t, the control input of multiplexer 3 (Fig. 25) contains a logical 1 signal, its operation is prohibited and despite the fact that all of its information inputs are FI f1

nor logical

output specified

the multiplexer is in a disabled state. In order for the trigger 6 in this case, when the output of the multiplexer 3 is not turned on, due to all sorts of pickups on the unconnected setup input, the output of the multiplexer 3 and the setup input of trigger 6 are connected to the device zero-potential bus through a resistor. As a result, during the time t ,, - t at the installation input of the trigger 6 there is a logic level O and its state does not change.

At the same time, during the time t - t, the signal of the logical O from the output of the pulse generator 1 is fed to the control inputs of the first key group 13, with the result that all the keys of the group 13 are open and their outputs are in the disabled state. At the same time, multiplexer 5 is enabled and one of its information inputs is connected to the output. However, since the outputs of the group of 13 keys are disabled and none of the switching elements of the matrix 4 is closed, in the considered time interval, none of

),

1585790. 6

its vertical bus signals from the logical 0 or logical 1 are not supplied and the inputs of the multiplexer 5 and its output are in the disconnected state. Since the output of multiplexer 5 through a resistor R is connected to the zero potential bus of the device.

then over time

on

ten

The installation input of the trigger 9 is a logic level O and its state does not change.

five

0

five

0

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five

For a time

H (second

half period) the signal of the logic 1 output of the pulse generator 1 (Fig. 2o () goes to the control inputs of the key group 13, as a result of which all the keys of the group 13 are in a closed state and their outputs present a logic level 1 (power supply voltage E) The indicated levels of logical 1 arrive simultaneously on all vertical buses of matrix 4 of switching elements and, accordingly, on all inputs of multiplexer 5. Since during a time a signal of logical 1 is applied to the control input of multiplexer 5, its operation is prohibited Since all its information inputs contain logic level 1, the output of the specified multiplexer is in a disconnected state. Connecting the setup input of the trigger 9 via the resistor R to the potential zero bus provides the device with a stable initial zero state when the output of the multiplexer is off five.

Simultaneously over time

t 3 the logical signal from the output of the element NOT 7 (Fig. 2) is fed to the control inputs of the second group 14 of keys, as a result of which all the keys of group 14 are open and their outputs are in the disabled state. At the same time, multiplexer 3 is enabled and one of its information inputs is connected to the output. However, since the outputs of the group of 14 keys are disabled and none of the switching elements of block 4 is closed, then in the considered time interval the logical signal

 O or logical 1 not given

and his exit

in the disabled state. Since the output of multiplexer 3 through

ta 0

and the multiplexer 3 inputs are

the resistor R is connected to the bus of zero potential of the device, then during

J on set time t t

The de trigger 6 has a logical level of 0 and it continues to be in its initial zero state. In the subsequent periods of pulses from generator 1 with open contacts of unit 4, the operation of the expansion of functional units occurs in a similar way.

In order that the positive differential at the inverse output (FIG. 2g) of the most significant bit of counter 2 (counter output) triggers b, 9, and 10 do not change their initial zero state, since the information inputs of these triggers contain logical O (for information the trigger input 10, a logic O signal is supplied from the output of the And 8 element, which, in turn, is due to the zero state of the triggers 6 and 9),

Consider the operation of the device when closing one of the contacts in the matrix 4. In the drawing (FIG. 2), the moments of the closing AND opening of one of the switching elements located in the general case on the i-th vertical and j-th horizontal tires are shown. Suppose that the closure of the switching element occurred in the time interval t -g when the counter 2 was in the ith state (Fig. 2). In addition, we assume that when closing and opening the switching element occurs bounce.

V. The time t on the trailing edge of the pulse from the output of the pulse generator 1, the counter 2 switches to the i state. From the description of the operation of the device, it follows that during t - t on all horizontal buses of the matrix 4 switching elements there are log levels 1 st and the output of multiplexer 5 switches its i-th input (i is the vertical bus of matrix 4). Consequently, if a switching element located on the i-th vertical bus of the matrix 4 closes in the specified time interval, a logical signal 1 (figs2e) is generated at the output of the lithi-hex.or 5 signal, under which the trigger 9 goes into one state (Fig. 2g). Put

The logical difference of logic levels arising at the output of the trigger 9 enters the synchronous input of register 11, as a result of which the binary register code of the vertical bus number (in this case i-th), on which the closed switching element is located, is written to register 11.

During the time ty-t, the level of logic 1 is present on all vertical buses of matrix 4 of switching elements, and the output of multiplexer 3 switches i-horizontal bus of matrix 4. Since the closed switching element is on j-th horizontal bus (J is not equal to i), then at the output of multiplexer 3, the logical 1 signal does not occur and the trigger 6 continues to be in the initial zero state.

0

five

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five

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tfi

Job

described by t.

During the time the device does not differ from the time interval t,.,. In this case, the trigger 9 continues to be in a single state, indicating that the code number of the vertical bus of the matrix 4, on which the closed switching element is located, is defined and stored in register 11,

During the time t - t. when counter 2 is in the jth state, logical level 1 levels from the outputs of the key group 13 are again supplied to all vertical buses of matrix 4, and its 3rd input is switched to the output of multiplexer 3 (j is horizontal bus of matrix 4). Since the closed switching element is on the j-th horizontal bus, in this case, the output of multiplexer 3 (Fig.2i, time t.,) Generates a logical signal, under which the trigger 6 goes into one state (Fig. 2 k), indicating that the code of the horizontal bus number on which the closed switching element is located is defined. A positive logical level difference occurring at the output of flip-flop 6 (FIG. 2 K) is fed to the synchronous input of register 12, as a result of which the binary code of the horizontal bus number (in this case, j-th), on which the closed switching element is written, is written to the specified register .

since time t triggers 6

and 9 are in the single state and at the output of the element And 8 there is a logical 1 (Fig.2i), arriving at the information input of the trigger 10,

At time t, by a positive differential of logic levels at the inverse output of the high bit of counter 2 (figure 2 g), the trigger 10 goes into one state (figure 2 / n and a logical signal 1 appears at the gate output of the device that the codes of the horizontal and vertical bus numbers, at the intersection of which the closed switching element is located, are determined and recorded in registers 11 and 12, i.e. the code of the closed switching element is formed and located at the information inputs of the device. triggers 6 and 9 go to the initial zero state.

In the following, the process of determining the code of a closed switching element is repeated. As long as the switching element in the matrix 4 is closed, the synchronous inputs of registers 11 and 12 at the corresponding moments of time receive pulses from triggers 9 and 6 (Fig. 2g and 2k, respectively), but the information on the outputs of the indicated registers (information outputs of the device) does not change, since the entry of information in registers 11 and 12 is performed under the same stable conditions of counter 2,

At time t after opening the contact in the matrix 4, the triggers 9 and 5 return to the initial state (fig. 2g, k) at the first positive differential at the inverse of the high bit of counter 2 (fig. 2 g), and at the next. the differential at the moment of time t, the resetting of the trigger 10 occurs (fig.2l). On the gating device, there will be a continuous, smooth signal that is used for further information processing.

In other possible situations of device operation, only the sequence of the occurrence of pulses from the outputs of multiplexers 5 and 3 and the triggering of flip-flops 6 and 9 changes, and the rest of the circuit operates in a similar way.

85790

In the general case, the matrix D of the switching elements is a matrix consisting of M 2

rows

ten

f5

20

25

thirty

35

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and L - 2 columns, at the intersection of which there are switching elements, where m is the number of bits of counter 2 necessary to form the binary codes of row numbers of matrix 4; 1 is the number of bits of counter 2 necessary to form the binary codes of the column numbers of block 4. Consequently, the width of counter 2 is determined by the maximum of the numbers and 1 (for a square matrix in which the number of rows and the number of columns are equal, m 1) The operation of the device (as follows from the description given) occurs in such a way that the interrogation of the switching elements is carried out in whole rows and columns.

FIG. Figures 3 and 4 show the cases when the delay time for the appearance of a positive (negative) front of a gating pulse relative to the closure (opening) of the switching element is maximum. FIG. For (4 ") shows the signal at the output of the generator 1 pulses; on Fig (4S) is the signal at the output of the element HE 7; in fig. Sv (4b) - signal at the output of the low-order bit of counter 2; in Fig. 3a, the signal at the inverse output of the higher bit of counter 2; in Fig. 3 (4) - a signal conditionally showing the moments of closing and opening of the switching element; in fig-. Ze (4 e) is the signal at the output of the multi-gateway 5; in fig. 3l; (4l;) - signal at the output of the trigger 9; in fig. Zi (4i) is the signal at the output of multiplexer 3; on figs (4k) - the signal at the output of the trigger 6; Fig with Zl (4l) - the signal at the output of the element And 8; in fig. Zm (4ll) - the signal at the output of the trigger 10.

FIG. 3 over time

t.-t

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counter 2 is in the first (initial) state. At the moment of time, the counter 2 goes into the next state, and practically from that moment of time the closure of the switching element is performed, the location of which in the matrix 4 is determined by the previous state), (during the time t;, - t) counter 2, i.e. the switching element is in the first column of the matrix and its closure occurs immediately after the counter 2 enters the second state, it is 10

determines the poll of the second column of the matrix. Consequently, at the output of the multiplexer 5, the signal of the logical 1 turns on only at the moment of time t (FIG. Ze). At time t, preceding time t, the signal of a logical 1 is given at the output of multiplexer 3. In this case, it is assumed that the closed switching element is on one of one of the lines, for example, j-th. The logical 1 signal at the output of the AND 8 unit at the Vits point at time tj, when the triggers 6 and 9 are in one state, and the trigger 10 trigger (the appearance of a strobe signal at the device output) occurs at the time t.

FIG. 4, a case is considered in which a closed switching element is in the first row and the first column of the matrix and opens when the counter 2 is in the initial state, which determines the interrogation of the first column and the first row of the matrix 4. of the switching elements. In this case, at the time of 15

20

t appears a logical 1 signal at the output of multiplexer 5 (fig. 4e) and flip-flop 9 triggers (fig 4). In fact, from the moment of time t-2, a logical 1 signal appears at the output of multiplexer 3 (Fig. Li) and the trigger 6 is triggered (Fig. 4k), during the time tj - tj at the output of the And 8 element (Fig.4l) the signal is logical 1, so that the time ment t, a positive differential level at the inverse output of the higher bit of counter 2 (FIG. 4 g) confirms a single state of the trigger 10 (FIG. 4L). At time t, triggers 6 and 9 return to the initial zero state, and then at time t4, trigger 10 returns to the original state.

In both cases, the maximum delay time for the appearance of the positive (negative) front of the strobe signal relative to the moment of closing (opening) of the switching element is approximately the same and is

t; (T - g) T, (1)

where T is the pulse following period from the inverse output of the high bit of counter 2;

The period is followed by the 1st impulse from generator 1.

 Considering that T is much larger than C, (O can be represented as

, 1, P) 1

Tumake-2T, 2

  .7 with. g

 -G. 2

where, 1} is the maximum of the numbers m and 1, which determines the number of bits of counter 2;

m is the required number of bits of counter 2 to form binary codes of row numbers of matrix 4;

1 is the required number of bits of counter 2 for generating binary codes of the numbers of columns of matrix 4.

Thus, the proposed device has a higher speed than the device on the proto - type.

Claims (1)

Invention Formula five 0 0 50 An information input device comprising a pulse generator, a counter, a first multiplexer, a matrix of switching elements, a first register, a first and second triggers, an AND element, a NOT element, a pulse generator output connected to the counter input, 5 outputs of the group of which are connected to information inputs of the first register and address inputs of the first multiplexer; information inputs of which are connected to vertical buses of the switching elements matrix, the output of the counter is connected to the synchronous inputs of the first and second triggers, the information input of the first trigger is connected to the zero potential bus, and the output is connected to the first input of the AND element, the reset inputs of the first, second flip-flop and the first register are the reset input of the device, the output of the second flip-flop is The sampling output of the device, the outputs of the first register are information outputs of the first group of devices, characterized in that, in order to increase the speed of the device, the second multiplexer, the third trigger, the second register, the first and second groups of keys, whose information inputs are entered into it plug 45 to the device power bus, the pulse generator output is connected to the control inputs of the keys of the first group and the first multiplexer and through the NOT element to the control inputs of the keys of the second group and the second multiplexer, the outputs of the keys of the first group -ra, the outputs of keys of the second group are combined with horizontal buses of the matrix of switching elements and connected to the information inputs of the second multiplexer, whose address inputs are connected to the information inputs The signals of the second register and the outputs of the counter group, the outputs of the second register are the information outputs of the second , 0 device groups, the output of the first multiplexer is connected to the installation input 1 of the first trigger, the output of which is connected to the synchronous input of the first register, the output of the second multiplexer is connected to the installation input 1 of the third trigger, whose information input is connected to the zero potential bus, the synchronous input of the third trigger is connected to the output the counter, the reset inputs of the third trigger and the second register are connected to the reset input of the first register, the output of the third trigger is connected. to the synchronous input of the second register and the second input element And, the output of which is connected to the information input of the second trigger. b TJOJ Editor E. Kopcha Compiled by I. Karpova Tehred L. Serdyukova Proofreader V. Girn to Order 2327 Circulation 571 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, 4/5 Raushsk nab Production and Publishing Combine Patent, Uzhgorod, st. Gagarin, 101 Fy Subscription