SU1495988A1 - Pulse switch with storage of control signal - Google Patents

Abstract

The invention relates to a pulse technique and can be used in devices for generating, issuing and processing information. The purpose of the invention is to expand the functionality by providing a pulse-switching inhibit mode. The key contains OR-NOT 1 ÷ 4 elements, inverter 5, input bus 9, control bus 10, output buses 11 and 12. Introduction of the element OR-NOT 6, trigger 7, mode bus 8, as well as the formation of a new set of connections provides pulse prohibit mode from input bus 9 to output buses 11 and 12.2i

Description

WITH

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FIG. one

The invention relates to a pulse technique and can be used in devices for generating, issuing and processing information.

The aim of the invention is to extend the functionality by providing a pulse-inhibiting mode from the input bus to the weekend.

FIG. 1 shows a functional diagram of a pulse key with control signal storage; in fig. 2 - timing diagrams explaining its operation.

The pulse key with the control signal memorization (hereinafter the key) contains the first to the fourth elements OR-NOT 1-4, inverter 5, fifth element OR-NOT 6, trigger 7, mode bus 8, input bus 9, control bus 10, first 11 and second 12 weekend tires.

Bus 11 is connected to the first input of the W1I-NOT 1 element, the output of the OR-NO 2 element and the first input of the OR-NO 3 element, the output of which is connected to bus 12 and the first input of the OR-NO 4 element, the second input of which is connected to iina 10, the output is connected to the second input of the IZH-NOT 3 element and the second input of the OR-NOT 1 element, the output of which is connected to the first input of the OR-NOT 2 element, the second input of which is connected to the third input of the 11ПИ-НЕ 3 element, S-input trigger 7 and the output of the inverter 5, the input of which is connected to the bus 9.. Bus 8 is connected to the R-input of the trigger 7, the output cat cerned is connected to the entry lane vomu OR-Hp 6, second and third inputs of which are respectively connected to buses 11 and 12, and an output connected to the third and fourth inputs respectively OR- NO elements 2 and 3.

In FIG. 2, signals 13 on bus 9, signals 14 on bus 10, signals 15 on bus 8, signals 16 on bus 11, signals 17 on bus 12 are indicated.

The key works as follows. In the initial state on bus 9 there is a level O, on buses 8 and 10 there can be arbitrary levels, for example levels O. In this case, the output of inverter 5 and trigger 7 has

levels 1 are inverted, at the outputs of the elements OR-NOT 2 and 3 and at the tires 11 and 12 - levels O

and 3 and tires 11 and at the outputs of elements

NOT 1 and 4 - respectively the levels O and 1, at the output of the element OR NOT 6 - level O.

Under the action of the leading edge of the pulse arriving at the bus 9, all the inputs of the 1CHI-NOT 2 element have O levels, and at its output a level 1 is formed, which is fed to the first inputs of the OR-NOT 1 and 3 elements and the bus 11 on which the leading edge of the output pulse, and the state of the remaining key elements does not change.

Under the action of the falling edge of the pulse on bus 9, the unit state of the trigger 7 is confirmed, the output of the OR-NOT 2 element and the first inputs of the OR-NOT 1 and 3 elements are set to O, and the back edge of the output pulse is formed on the bus 11. In this case, the key returns to its original state.

If at the time of the pulse on bus 11, bus 10, the control signal level changes from 0 to 1, this does not have any effect on the condition of tires 11 and 12 5 because the signal level change at the output of the OR-NO 4 element caused by changing the control signal on bus 10 does not affect the state of the elements of the IPI-NE 1 and 3, which are blocked at this time by level 1 from bus 11. From this it follows that the key remembers the control signal on bus 1C at the time of the beginning and for the whole time switching impulses from bus 9 to bus 11.

Thus, if there are O levels on buses 8 and 10, then the impulse fed to bus 9 is switched, keeping the duration on bus 11, and on bus 12 O level is saved and, therefore, the key is installed on bus 8 to pulse switching. If at the same time on the bus 10 a change in the level of the control signal occurs at the time of the pulse on the bus 11, this does not lead to a change in the state of the tires 11 and 12 and therefore does not distort the bus pulse 9 on the bus 11.

Suppose that in the initial state of the key on tires 8 and 10 there are respectively levels O and 1. In this case, at the output of trigger 7 there is level 1, at the outputs of EGSh-HE elements 2 and 3 and tires 11 and 12 are levels O,

five

the output of the elements OR NOT 1 and 4 are levels 1 and O, respectively; the output of the element OR NOT 6 is level O.

Under the core of the front pulse on bus 9 at all inputs of the element OR OR NOT 3 there are levels O, and at its output a level 1 is formed, which goes to the first input of the element OR NOT 4 and bus 12, on which the leading front of the output impulse, and the state of the remaining key elements does not change.

Under the action of the falling edge of the pulse on bus 9, the unit state of the trigger 7 is confirmed, at the output of the OR-NO 3 element and the first input of the OR-NO 4 element a level O is set, and on the bus 12 a back edge of the output pulse is formed. In this case, the key returns to its original state.

If at the time of the pulse on bus 12 on bus 10, the level of the control signal changes from 1 to 0, this does not affect the condition of tires 11 and 12, since the output level of the OR-NO 4 element does not change the signal level, . as this element is blocked at this time by the level 1 from the bus 12. From this it follows that the key memorizes the control signal on bus 10 in the beginning and for the whole time of the pulse switching from bus 9 to bus 12.

Thus, if on buses 8 and 10 there are levels O and 1, respectively, then the impulse fed to bus 9 is switched while maintaining the duration on bus 12, and on bus 11 the level O is saved, and, successively, the key is installed on bus 8 pulse switching mode If a change in the control signal level in the bus Ip occurs; the moment of a pulse on bus 12 does not cause a change in the state of the psn 11 and 12, and therefore does not distort the bus impulse 9 on the bus 12.

Let in the initial state on shi

Not 8 there is a level 1, but on bus 10 there is an arbitrary logic level. Moreover, since in the initial state, the output of the inverter 5 operates at the level, then at the outputs of the elements OR NONE 2 and 3 and buses 11 and 12. the levels O act, and at both inputs

0

five

0

five

trigger 7 there are levels 1. As a result, at the output of trigger 7 and element 11LI-NOT 6, levels O and 1, respectively, the last of which goes to the third and fourth inputs of the elements OR-NOT 2 and 3, respectively, and blocks them. The supply of pulses to bus 9 in this mode does not change the signal level at the output of flip-flop 7, since its R-BXO continuously operates level 1 received from bus 8. As a result, the output of the OR-HE element 6 continues to operate level 1 which does not allow the condition of tires 11 and 12 to remain at which levels O are maintained,

Thus, if bus 8 has a level 1, and bus 10 has an arbitrary logic level, then the pulses arriving on bus 9 are not passed to buses 11 and 12 and, therefore, the key is installed on bus 8 to the impulse-switching mode. .

If the key is transferred via bus 8 from the pulse switching mode to the cog-mutation prohibition mode at that moment when an output pulse is formed on one of the buses 11 or 12, as a result, at the output of trigger 7, level 1 changes to level A. However, at the output of the element OR-NOT 6, the signal level continues to remain equal to O, since this element is blocked at this time by level 1 at its second or third input (depending on which bus 11 or 12 is on - output pulse).

On the falling edge of the pulse on bus 9 at all inputs of the element OR NOT 6 there are levels O, and at its output

five

0

1, which is block

with and there are levels

a level is formed, which is kocking elements ISH1-HE 2 and 3 at the third and fourth and fourth inputs, respectively. Further operation of the key when pulses are received on the bus 9 is similar to that specified in the prohibition mode. pulse switching.

Thus, if the key is transferred over the bus 8 from the pulse switching mode to the switching prohibit mode. At the moment when one of the buses, 11 or 12, an output pulse is formed, this does not affect the condition of the buses 11 and 12, and sledova5

It does not distort the duration of the com- muted pulse on the corresponding output bus.

If the key is transferred via bus 8 from the commutation inhibit mode to the Pulse switching mode at the instant of a pulse on bus 9, then ijare as a result of both inputs of trigger 7. There are levels O. Since this combination of input signals is a neutral trigger and determines the storage mode recorded in it 1: information, then the output of the trigger 7 t; of the element OR-NOT 6 continue to preserve 1 levels, respectively. In this case, the elements are OR-EE 2 and 3 Despite the change that has occurred: the signal on bus 8 remains blocked by the third and fourth inputs, respectively, and the levels of 0 on the pins 11 and 12 remain. IO pulse edge on bus 9 is on high: Trigger code 7 is set to level 1, and at the output of the HIlIi-HE B element, the O level is set. Further operation of the switch when pulses are received on iJMHy 9 is similar to that specified in the Pulse switching mode.

Thus, if the key is transferred over the bus 8 from the Switching prohibit mode to the pulse switching mode at the moment bus 9 is in operation, this does not affect either the bus condition 11 and 12, j t.e. does not lead to the formation of their output pulse with a shortened duration in relation to the duration of the pulse on the bus 9.

Claims (1)

Invention Formula A pulse key with a memory of the control signal containing the first output bus, which is connected to the first input of the first element OR NOT, the output of the second element OR — NOT, and the first input of the third element OR — NOT, the output of which is connected to the second output bus and the first the input of the fourth element OR-NOT, the second input of which is connected to the control bus, the output of the fourth element 1SHI- NOT connected to the second input of the third element OR-NOT, the output of the first element OR-NOT connected to the first input of the second element OR-NOT, the second entrance to third is connected to the third input of the third element OR NOT and the output of the inverter, whose input is connected to the input bus, the third input of the second element OR NOT is connected to the output of the fifth element OR NOT and the fourth input of the third element ILN-NOT, that, in order to expand the functionality due to the provision of the pulse-disabling mode from the input bus to the weekend, a trigger was entered into it, the reset input of which is connected to the mode bus, the trigger start input is connected to the output of the inverter, the output: the trigger is connected But the output of the fourth element OR-NOT is connected to the second input of the first element OR-NOT. LF,. -VA J -ki "about J