SU1644283A1 - Device for protection of self-contained inverter - Google Patents

Abstract

The invention relates to electrical engineering and can be used to protect an autonomous inverter. The purpose of the invention is to expand the functionality of the device for protection. Current sensor 1 is enabled at the input of the inverter. Differentiating element 2 generates pulses with each switching keys. If the switch-off time of the key exceeds the setting of the delay element 3, a logical zero is generated at the output of the NAND 4 element. If the time interval from the moment of supplying the control pulse from the control system to the moment of commencement of switching exceeds the setting of the delay element 7, a logical zero is formed at the output of the AND-HE element 8. In case of any malfunction of the inverter at the output of the NAND 9 element, a malfunction signal is generated. The device provides protection against loss of control of the inverter keys. 1 silt

Description

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The invention relates to electrical engineering and can be used to protect stand-alone inverters, for example, in AC electric drives.

The aim of the invention is to expand the functionality.

The drawing shows a functional diagram of a device for protecting an autonomous inverter.

The device contains a current sensor 1, included in the DC link at the input of the inverter. The output of current sensor 1 is connected to the input of differentiating element 2. The output of the latter is connected to one, and through the first delay element 3 to the other input of the first element NAND 4, and to the input of the element NO 5, the output of which is connected to the inverse R input O- trigger 6, in which the D- and inverse S-inputs are connected to the bus logical unit, and the output is connected to the output of the control system, which pulses to turn off the next key of the autonomous inverter, the output of the D-trigger 6 is connected to one, and through the second delay element 7 and with other entrances torogo I- NOT element 8, whose output is connected to the first input of the third AND-member 9, a second input coupled to an output of first AND-NO 4.

The device works as follows.

In the absence of emergency modes when an autonomous inverter is in operation, each time the power switch is turned off, the current in the DC link at the input of the inverter changes almost abruptly by the amount of current flowing through the switchable key. Differentiating element 2 at this moment gives a short signal

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level, logical unit, and duration, equal to the time the key is turned off. The rest of the time, differentiator 2 produces a logical zero. The first delay element 3 delays the passage of a logical unit for a time equal to the maximum possible shutdown duration of the sieve key, so in normal operation of an autonomous inverter, the first element AND-NOT 4 outputs a logical unit. Each shutdown of the power switch is preceded by a pulse emitted by the autonomous inverter control system and fed to the dynamic C input of the D-flip-flop b. The leading edge of the pulse, the D-flip-flop, is transferred to the state when a logical unit appears at its output. After a time corresponding to the passage of the switching off pulse through the control channel to the power switch and the beginning of switching off the latter, relative to the leading edge of the pulse emitted by the control system of the autonomous inverter, a logical unit appears at the output of differentiating element 2, and logical zero, which translates the D-flip-flop b to the logical zero state. The second delay element 7 delays the passage of a unit by the time corresponding to the maximum delay time for switching off the power switch relative to the leading edge of the pulse, through which the power switches to the dynamic C input of the D-trigger 6 are turned off. Therefore, during normal operation of the inverter at one of the inputs The element AND-NE 8 is always a signal corresponding to a logical zero, and the output is a logical one. Thus, at both inputs of the third element IS-HE 9 there are ones, and the output is a logical zero corresponding to the normal operation of the autonomous inverter.

In the case of a short circuit, the duration of a logical unit from the output of differentiating element 2 is longer than the delay time of the first delay element 3, at both inputs of the first element IS-NE 4 a logical unit appears, and at the output a logical zero translating the third element IS-HE 9 into state of the logical unit corresponding to the state of the accident.

If the power switch is not open, although the signal to open it was issued, after the appearance of a pulse, on the leading edge of which the key is turned off, differentiator 2 does not produce a logical unit. This is explained by the fact that, by the switch-off signal, the current in the DC link will continue to flow without an abrupt change, since

key was not included. D-trigger b on the leading edge of the pulse arriving at the C input. will be transferred to the state of a logical unit, and will not be reset to zero due to the lack of a signal to turn off the key. Therefore, after a delay time determined by the second delay element 7, two inputs of the second element IS-NE 8 are applied to each unit, the output of the IS-NE 8 is set to a logical zero, which

will transfer the third element AND-NOT 9 to the state of a logical unit corresponding to the accident,

Claims (1)

Invention Formula A device for protecting an autonomous inverter equipped with a control system containing a current sensor for connecting to the input of a protected inverter connected to the input of the differentiating element, the first delay element, the AND-NOT element and the NO element, characterized in that, in order to extend the functionality, a D-trigger, a second delay element, the second and third AND-NOT elements are introduced, and the output of the differentiating element is connected with the first input of the first element AND-NOT directly, with its second input through the first element delays, and with the inverse reset input of the D-trigger through the NOT element. the D-flip-flop input is designed to connect to the output of the control system of the protected autonomous inverter, the information and inverse setup inputs of the D-flip-flop are designed to connect the potential of the logical unit to the source, the D-flip-flop output is connected to the first input of the second element AND –NE directly, with its second input through the second delay element, while the outputs of the first and second elements AND-NOT are connected to the inputs of the third element NAND, the output of which is used in as the output device. % de 1st ZZ. Ir1 L i-u 1st H-Ht From the control system Tire. logical effes / scts 3rd To cue topic g 2nd twe 8 gi a-rj : ulra & le. Wltff