SU1610537A1 - Device for protecting d.c. motor against excessive reversing frequency - Google Patents

Abstract

The invention relates to electrical engineering and can be used to protect DC motors in reverse mode. The aim of the invention is to extend the functionality by protecting against an unacceptable increase in the frequency of reversal. When the control signal arrives at the input of the device, the signal from the output of the AND 2 element transfers the RS flip-flop to the logical "0" state, the signal from the inverse output of the flip-flop is differentiated by the differentiator 7 and is formed by the OR-NO 8 element, sets the counter 9 to the initial state. From this moment, its filling from the generator 10 begins. At the time of filling the counter, the logical "0" signal from its output, inverted by inverter 11, together with the signal from the inverse output of the trigger 5, switches the logical element 3 to the logical state "0", which prohibits passing the signal from the input of the device to the input of the power amplifier 14, which will lead to a change in the frequency of the reversal of the engine to an acceptable value. 2 Il.

Description

The invention relates to electrical engineering and can be used to protect DC motors in reverse mode.

The purpose of the invention is to enhance the functionality by protecting against an unacceptable increase in the frequency of reversal.

FIG. 1 shows a functional diagram of the device; in fig. 2 - timing charts that explain his work.

The device contains from the first to the fourth logic elements AND 1-4, RS-flip-flop, two differentials 1, 6 and 7, connected by outputs to the inputs of the element OR-NOT 8, the inverse output of which is connected to the input of the installation in O of the counter 9 pulses, a reference frequency generator 10 connected by a code to a clock input of a pulse counter 9, the output of which through the first inverter 1 is connected to one input of the third 3 and fourth 4 AND elements, the inverse outputs of which are connected respectively to one input of the first 1 and second 2 AND elements, others to toryh device are input, the second 12 and third 13 inverters, incl chennye inverted outputs, respectively, between the first 1 and second 2-input AND gates and power amplifier 14.

The device works as follows.

In the initial position, the state of the outputs of the trigger 5 is arbitrary, on the inverse output of the element OR NOT 8

the inverter 11 is a logical O. Accordingly, at the outputs of the And 3 and 4 elements there is a logical 1, which does not prevent the passage of control signals when they appear at the input of the device 15 and 16 through the elements 1,2 and 12,13 to the inputs of the power amplifier 14 .

When the input signal 17 arrives at the input 15 from the output of the pulse-width modulator in the automatic engine control system, the signal from the output of the And 1 element switches the RS-flip-flop 5 to the logical 1 state (signal 18), the signals 19 and 20 from the flip-flop 5 outputs Differentiators 6 and 7 are differentiated, the output signals 21 and 22 of which are fed to the inputs of the OR-NOT 8 element, the output signal 23 of which sets the counter 9 to the initial state at the output logical O (signal 24). From this moment on, the filling of the counter 9 from the generator 10 begins. The filling time of the counter determines the allowed frequency of reversal. On

the filling time of the counter 9 at its output is acted upon by a logical O signal (signal 24), which is inverted by an inverter 11 (signal 25) and together with a signal from a direct code

5, the trigger 5 translates the element 4 into a state of logical 0 (signal 26). This signal blocks the passage of the control signal 27 from the input 16 of the device to the input of the power amplifier 14 for the duration of the counter 9 (signal 28).

When the control signal 27 arrives at the device input 16, the signal 29 from the element ID 2 switches the RS5 trigger to the logical state O, the signal from the inverse trigger code is differentiated by differentiator 7 and is formed by the element OR-HE 8, the counter 9 is set

0 state (output logic O). From this moment, the filling of the counter 9 from the generator 10 begins. At the time of filling the counter, the logical O signal from its input, inverted by the inverter 11, together with the signal from the inverted output of the trigger 5 transfers the logical element 3 to the logical O (signal 30), which prohibits the passage of the signal from the input 15 of the device to the input of the power amplifier 14 (sig-on 31).

Thus, at the permissible frequencies of reversals, devices for g ambient does not affect the operation of the power amplifier. If the frequency of the engine reversal begins to exceed the permissible value, then the protection changes the frequency of the signal reversal at the engine input to the permissible5

0

0

five

that value.

Claims (1)

Invention Formula A device for protecting a direct current motor from exceeding the permissible reversing frequency, containing an RS flip-flop, the first And element, one of the inputs of which is one input of the device, the second And element, the reference frequency generator connected by the output to the pulse input of the pulse counter, and the executive An organ, characterized in that, in order to increase reliability, three inverters, two differentiators, the third and fourth AND elements and the OR-NOT element are additionally introduced, and the executive body is designed as an amplifier POWER, while the output of the pulse counter through the first inverter is connected to the first inputs of the third and fourth elements AND, the codes of which are connected respectively to another input of the first element AND and to one input of the second, element AND, the other input of which is the second input of the device, the output of the first element And is connected to the S-input of the RS flip-flop directly sy ereot- 10 via the second inverter to one of the inputs of the power amplifier, the output of the second element I is connected to the R input of the RS flip-flop directly and through the third inverter to the other input of the power amplifier, the direct RS-trigger trigger is connected to the second input the fourth element And directly and through the first differentiator - to one input of the SHS-NOT element; the inverse output of the RS flip-flop is connected to the second input of the third element And directly and through the second differentiator to the other the input of the OR-NOT element, the output of which is connected to the input of the installation in O of the pulse counter, the inputs of the installation of the division factor of which is connected to the buses specifying the logical zero and logical unity. 20 (frevers ct Jdon} (frevers.: fffo