SU1741247A1 - Dc electric drive - Google Patents

Abstract

Usage: in an automated DC electric drive. SUBSTANCE: electric drive contains electric motor 3, power amplifier 2, key 1, controlled by reversible counter 14. Introduction of the first 11 and second 12 delay lines, RS flip-flop 10 and first 17 and second 13 elements 2 OR ensures the prevention of failures in the controlled reversing counter 14, and this increases the reliability of operation and reduces energy consumption. 1 Il.

Description

The invention relates to electrical engineering and can be used in an automated electric drive for stabilizing the frequency of rotation of DC motors.

A known DC motor includes a motor connected to the output of a power amplifier, a speed sensor, a master oscillator, a reversible counter, two short pulse formers, four NAND units, two inverters, the master oscillator through the first short pulse driver and the first element NID is connected to the subtracting input of a reversible counter, the summing input of which is connected via the second element NAND and the second driver of short pulses with a speed sensor, the outputs are reversible of the counter via inverters connected to the inputs of the third AND-NO element whose output is connected to the input of the first AND-NO element,

the output of the second inverter is connected to the input of the power amplifier, the outputs of the reversible counter through the fourth element AND-NOT connected to the input of the second element AND-NOT.

The disadvantages of this device owner. with high power consumption caused by the use of TTL microcircuits, and low speed.

The closest technical solution to the present invention is a DC electric drive comprising a key connected in series, a power amplifier, an electric motor, a rotational speed sensor, as well as a master oscillator, the output of which is connected to the first input of a programmable frequency divider whose output is connected to the input the first shaper of short pulses, the output of which is connected to the input of the first element 2I. the first input of the second element 2I is connected to the output

Yo

sj

Јw

one

U 4 CHK

the second short pulse generator, the input of which is connected to the output of the rotational speed sensor and to the input of the period-code converter, the first inputs of the comparator are connected to the inputs of the programmable frequency divider and the outputs of the reference period code generation unit, the second inputs of the comparison device — with the period converter outputs code, reversible counter, the first and second outputs of which are connected to the first and second inputs of the third element 2I, inverter, one-shot, the input of which is connected to the output of the device with equal, and the output of the one-shot is connected to the setup input of the reversible counter

The disadvantages of this device are device malfunctions due to the possibility of simultaneous arrival of pulses at the inputs +1 and -1 of a reversible counter, since for normal functioning of reversible counters of the TTL series it is necessary at the moment of arrival of the pulse to one of the inputs +1 or - 1 at another input, to fix the level of the Log. The influence of the comparison device on the stabilization mode in the synchronous operation mode of the electric drive, since only the value of the rotation frequency of the engine becomes less than the required one, the comparison device blocks the operation of the reversible counter and connects the electric motor to the mains, which disrupts the rotational frequency stabilization mode with proportional control of the average motor supply voltage as a function of the error angle between the pulses of the programmable frequency divider and the rotational speed sensor; when working on signals of different amplitude during acceleration, the electric motor has different excess energy at the moment of equality of the set and used speed. Therefore, the time impulse required for the excess energy potential must be different for different signals; low profitability due to the presence of TTL chips (reversible counter).

The aim of the invention is to improve the reliability of the system by preventing malfunctions.

The goal is achieved by the fact that the DC motor contains a key connected in series, a power amplifier, an electric motor, a rotational speed sensor, and a master oscillator, the output of which is connected to the input of the first short pulse generator, the output of which is connected to the first input of the first element

2I, the first input of the second element 2I is connected to the output of the second shaper. short pulses, the input of which is connected to the output of the rotational speed sensor and

the period-code input to the converter, the first inputs of the comparison device are connected to the inputs of the programmable frequency divider and the outputs of the task period code generation unit, the second inputs of the device

0 comparisons are connected to the outputs of the period-code converter, a reversible counter, the first and second outputs of which are connected to the first and second inputs of the third element 2I, the inverter, the first and

5 second delay lines, RS-flip-flop, first and second 2IL elements, the second outputs of the first and second short pulse shapers connected to the second inputs of the second and first elements 2I, respectively, the first output of the comparator is connected to the zero input R of the reversible counter, the second the output of the comparator is connected to the enable input of the preset PE reversing

5 of the counter, the second output of the reversible counter is connected to the key input, and the transfer output CO is connected via the inverter to the first input of the first element 2OR. the output of which is connected to the second input

0 of the third element 2I To the output of the first element 2IL there is connected the enable input of the CI account of the reversible counter, the first and second elements 2I are connected to the S and R inputs of the RS flip-flop, respectively, and through

5 delay lines to the second element 2IL, the output of which is connected to the clock input of the reversible counter. The output of the RS flip-flop is connected to the input of the installation of the counting direction Ј1 of the reversible counter. The first, third, and fourth inputs of the preset reversible counter are connected to the common bus of the device, and the second to the voltage bus of the litany.

The drawing shows an example of a specific device execution

The electric drive contains a series-connected key 1, a power amplifier 2, an electric motor 3, a rotational speed sensor 4, and also a master oscillator 5,

0 whose output is connected to the first input of a programmable frequency divider 6, the output of which is connected to the input of the first short pulse shaper 7, the first output of which is connected to the first input of the first element 2I 8, and the second to the second input of the second element 2I 9, Element Outputs 8 and 9 are connected respectively to the S and R-inputs of the RS flip-flop 10 and through the delay lines 11 and 12 to the inputs of the second element 2 OR 13. whose output

connected to the clock input C of the reversible counter 14. The output of the RS flip-flop 10 is connected to the input of the installation of the counting direction +1 reversible counter 14, the outputs of which are connected to the inputs of the third element 2I 15 and one of the outputs to the input of the key 1. Reverse transfer output CO of the reversible counter 14 through the inverter 16 is connected to the first input of the first element 2ILI 17, the second input of which is connected to the output of the third element 2И 15. The output of the first element 2ILI 17 is connected to the counting resolution input CI of the reversing counter 14. The drive also contains a photo unit Set the period code of task 18, the outputs of which are connected to the inputs of a programmable frequency divider 6 and the first group of inputs of the comparison device 19, the second group of inputs of which are connected to the outputs of the period-code converter 20, and the first and second outputs are connected respectively to the zeroing input R and input preset PE reversible counter 14. The output of the speed sensor 4 is connected to the inputs of the converter period-code 20 and the second shaper of short pulses 21 the first and second outputs of which are connected with Enikeev second inputs 9 and the first 8 elements 2I.

The first D1, third D3 and fourth D4 inputs of the preset reversible counter 14 are connected to the common bus of the device, and the second input D2 to the supply voltage bus.

Reversible counter 14 is implemented on the basis of the K-MOS counter 564IE11, which has the input of the installation of the counting direction +1 and the clock input C, on arrival of which the pulse counter, if the account is allowed, either adds one (if ± 1 equals Log.1), or subtract (if + 1 is equal to Log.O).

The drive works as follows.

When the direct current drive is turned on, the comparison device 10 compares the feedback period code from the period-code converter 20 with the reference period tolerance codes that the comparison device forms when receiving the reference period code from the reference period code generating unit .

The limits of the tolerances are determined by the speed of the engine. The smaller the engine time, the less tolerances can be.

Since the upper bound of the code Tzadtah of the period of the pulse following the setpoint is less than the code of the feedback period

Tos, at the second output of the comparator 19, a level Log.1 occurs, which writes to the reversible counter 14 on the first bit 0, on the second one - 1. Log.1 from the second output of the reversing counter 14 through the key 1 and the power amplifier 2 connects the electric motor 3 to the network. The speed of the electric motor 3 begins to increase. As soon as the code of the feedback period, the Tos will be less than the code of the upper bound of the TEEDtah code. at the second output of the comparison device 19, a Log.O appears, which allows the reversing counter 14 to count the pulses from the short pulse shapers 7 and 21. When a pulse arrives from the programmable frequency divider 6, the first short pulse shaper 7 forms a short pulse on the leading edge. The second output of the short pulse generator 7 is inverse with respect to the first one and during the action at the first pulse output, the level of Log.O from the second output blocks the second element 2 and 9, prohibiting the pulse from the second short pulse generator 21 from this time.

The shapers of short pulses 7 and 21 are one-shot, and the duration of the pulses generated by each of them must be equal. This prevents malfunctions caused by the simultaneous arrival of the pulses of the first 7 and second 21 shapers of short pulses. Moreover, if at the moment of presence of a pulse at the first output of one of the formers, a pulse arrives from the other, then after the first pulse ends, the blocking is released and the second pulse of the other generator passes to the trigger 10 and the reversing counter 14. There is no loss of pulse.

Pass through the first element 2 and 8. at the second input of which with the inverse output of the second shaper 21 short pulses level Log.1. this pulse sets 1 RS flip-flop 10 and, via delay line 11 and element 2ILI 13, adds one to the reversing counter 14. The code becomes 0011. The electric motor continues to increase speed. When a short pulse arrives from the second generator 21, the pulse sets the RS-flip-flop 10 to the zero position through the second element 2I and through the delay line 12 and the element 2IL 13 reversing counter 14 to the state 0010. As soon as the motor speed is greater than the required one, the moment of arrival two pulses from the rotation speed sensor in the absence of the pulses of the first short pulse pulse during this time. A code 0001 is generated at the output of the counter, and the electric motor begins to brake. The motor will operate in a mode of stabilizing the rotational speed with proportional control of the average power supply of the engine as a function of the error angle between the pulses of the programmable frequency divider and the frequency of the rotational sensor.

In order to prevent the reversal counter 14 from being transferred from the state of all zeros to the state of all ones, the transfer output of the reversible counter 14 through the inverter 16 and the first element 21LL1L17 is connected to its counting enable input C. Once in the subtraction mode at the counter outputs 14 will be a zero code, at the output of the transfer C the level of the Log.O will be set, at the output of the inverter 16 the level of the Log. 1, which, through the first element 2IL 17, prohibits further counter operation in the pulse subtraction mode. Similarly, when working on addition and if code 0011 exits the counter, the counter operation on addition through element 2I15 and element2 OR 17 occurs if the rotation speed of the electric motor increases so that the minimum the tolerance code of the reference period T3ad will be greater than the rotational speed sensor period code, at the first output of the comparator device 19 a level Log.1 occurs, which will reset the reversible counter 14. The signal Log.O from into the second output of the reversible counter 14 disconnects the motor from the network. The motor starts to brake.

The transition from one frequency to another is similar to the above. Note that this device uses a directly proportional linear period-code converter, in which a larger code corresponds to a larger period. From the task period code generation unit, there is also information in which a larger code corresponds to the required period.

As the comparison device 19, a single-chip microcomputer of the 1816 series can be used.

The required tolerance values of the task period code are set by the corresponding programming of a single-chip microcomputer.

As a delay line, it is possible to use two series-connected 564LN2 inverters. In this case, the delay of signal propagation through the RS flip-flop will be less than the delay of the passage of this signal by

the clock input of the reversible counter 14. therefore, first upon arrival of the pulse, the RS-flip-flop is set to the required state and the required counting direction of the reversible counter is set, then this pulse arrives at the clock input of the reversible counter and counts in the right direction

Claims (1)

Invention Formula A DC motor containing a motor connected to the output of a power amplifier whose input is connected to the output of a switch rotational frequency, as well as the master oscillator, the output of which is connected to the first input of a programmable frequency divider, the output of which is connected to the input of the first short pulse generator, the output of which is connected to the first input of the first element 2I, the first input of the second element 2I is connected to the output of the second short pulse generator, the input of which is connected to the output of the rotational speed sensor and to the input of the period-code converter, the first inputs of the comparator are connected to the inputs of the programmable frequency divider and the outputs of the job period code generation unit, the second inputs of the comparator are connected to the outputs of the period-code converter, a reversible counter, the first and second outputs of which are connected with the first and second inputs of the third element 2I, inverter, characterized in that, in order to increase reliability, the first and second delay lines, the RS flip-flop, the first and second 2IL elements, and the second outputs of the first and second the short pulse drivers are connected to the second inputs of the second and first elements 2I, respectively, the first output of the comparison device is connected to the zeroing input R of a reversible counter. the second output of the comparator is connected to the preset enable input PE of the reversible counter, the second output of the reversible counter is connected to the key input, and the transfer output CO is connected to the input of the inverter, the output of which is connected to the first input of the first element 2IL, to the second input of which the output of the third element 2I is connected, the output of the first element 2 OR is connected to the input enable CI reversible counter, the output of the first element 2I is connected to the input of the first delay line and to the S input of the RS flip-flop, the output of the second element 2Y is connected to the input of the second delay line and to the R input of the RS flip-flop, output of the RS flip-flop connected to the input of the installation of the counting direction ± 1 reversible counter, the clock input of which is connected to the output of the second element 2ILI, the first and second inputs to the code of the first and second line of the third, third and fourth inputs of the reversing counter by the common bus of the device, and They are connected respectively to the output voltage of the bus. the first and second delay lines, the first, third and fourth preset inputs of the reversible counter are connected to the common bus of the device, and the second input is connected to