SU1503055A1 - Device for separate control of reversible thyristor converter - Google Patents

Abstract

The invention relates to electrical engineering, in particular, to converter technology, and can be used to control the switching of groups of reverse thyristor converters with separate control. The purpose of the invention is to increase the reliability of separate control in transient conditions with a current-free pause. The device contains two two-threshold comparator 1, 2, null-organ 3, shaper 7 pauses, performed on logical inverters 8, 9, elements AND NOT 10-12, element AND and multivibrator 14, two symmetrical control channels 15, 16, made on mainly 17 and an additional 18 flip-flops, an eight-input AND-OR element 33, inverters 21, 22, AND elements 23-25, AND-NOT elements 29-332, and OR elements 26-28. Achievement of the goal is ensured by the introduction of additional AND-NOT elements 34 - 36, elements 38, 39, inverter 40, two elements OR 41, 42, and a change in the connections between steel elements. 4 il.

Description

l

sd about 00

about

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31501055

in transient modes with dead-pause. The device contains two two-threshold comparators 1, 2, null-organ 3, shaper 7 pauses, performed} ia logic inverters 8, 9, elements 10-12, element And and multivibrator 1D, two balanced control channels 15, 16, performed

the triggers, the eight-input element AND-OR 33, the inverters 21, 22, the elements AND 23-25, the elements AND-NOT 29-32 and the elements SHSh 26-28. 71 the goal is achieved by the introduction of additional elements H-NOT 34-36, elements 38, 39, inverter 40, two elements 1111, 42 and a change in the connections

mainly 17 and an additional 18 10 between a number of other elements. 4 il.

The invention relates to electrical engineering, in particular, to converter technology, and can be used to control the switching of groups of reverse thyristor converters with separate control.

The purpose of the invention is to increase the reliability of separate control in transient conditions with a current-free pause.

FIG. 1 shows a functional diagram of a device for separate control of a reversible thyristor converter; FIG. 2 shows an example of including the device in a direct current drive circuit} FIG. 3 shows voltage and current diagrams

The device {in FIG. 4 shows the time diagrams of the operation of the device.

A device for separate control of a reversible thyristor converter, contains two two-threshold comparators 1 and 2 and a null organ 3, inputs 4-6 of which are inputs of the device and are connected to the sources of the error reference signal and load current, respectively, a pause generator 7 containing two inverters 8 and 9, three elements AND-NOT 10-12, element AND 13 and multivibrator 14, the inputs of the first two elements AND-NOT 10 and 11, as well as the input of the first inverter 8 are connected to the corresponding para-f outputs of the second two-threshold com Arator 2, while the upsurge of the first inverter 8 is connected to another input of the second element AND-NO 11, the outputs of both elements AND-NO 10 and 11 are connected to the inputs of the third element AND-NO 12, which is connected with its output to the first input of element And 13, output which is connected to the input of the multivibrator 14, and the output after

0

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five

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it is with the input of the second inverter 9, and the outputs of both are paraphase outputs of the shaper 7 pause, two symmetrical control channels 13 and 16, each of which contains the main 17 and auxiliary 18 RS triggers, while the forward outputs 19 and The 20 main RS flip-flops 17 are outputs of the device, two inverters 21 and 22, three elements AND 23-25 and OR 26-28, four AND-NOT 29-32 elements, and also AND-OR 33 element, the first input being the first two elements And 23, 24, the first element ICI 26 and the element AND-OR 33, as well as the fifth input of the last one and both of the inputs the second element ENTA 27 is connected to the corresponding paraphase outputs of the first two-threshold comparator 1, the first input of the third element AND 25, the first element AND-NOT 29, the input of the first inverter 21, and the third input of the second element AND 24 and the seventh input of the element AND-OR 33 are connected to corresponding paraphase outputs of the second two-threshold comparator 2, the second input of the first element AND-NOT 29 and the input of the second inverter 22 are connected to the outputs of the zero-organ 3, and the third input of the first element AND-NOT 29 - with the output of the second element OR 27, the second inputs of the third element and AND 25, a second AND-NO element 30, and second and third inputs of the AND 13 paused formers 7 are connected to the corresponding. directing and inverse outputs of the auxiliary RS-flip-flops 18 of both channels 15 and 16, with the fourth input of the element And 13 of the former 7 pause connected to the output of the second inverter 22, the paraphase outputs of the former 7 of the pausing And 24 and element AND-OR 33, and also with the eighth

the input of the last one, the phmsil of the above mentioned elements are connected to the inputs of the third element of the IPI 28, connected by a third output to the third input of the AND-31 element, the other input of which is connected to the output of the first ISh 26 element, the second input of which is connected with the output of the first element And 23, the second and third input of the last connected to the outputs of the first inverter 21 and the fourth element AND-NOT 32, respectively, the inputs of which are connected to the outputs of the second element AND-NOT 30 and the third element And 25, and another input of the second element And - NOT 30 connected with the output of the second inverter 22, and the output of the first inverter 21 - with the corresponding inputs of the element AND-OR 33, the second element AND 24 and the first element AND-NOT 10 driver 7 power, the fifth, sixth and seventh elements AND-NOT 34-36, fourth, fifth and sixth elements AND 37-39, third inverter 40, fourth and fifth elements OR 41 and 42, with the first element AND-HE 29 provided with an additional input connected to the inputs of the fourth elements OR 41, And 37, the sixth element AND-NO 35, as well as with the input of the third inverter 40 and the output of the fifth element AND-NOT 34, the first three inputs of which go is connected to the corresponding outputs of both two-threshold comparators 1 and 2 and the zero-organ 3, and the other two to the inverse output of the auxiliary RS-flip-flops 18 of both channels 15 and 16, while the output of the third inverter 40 is connected to the input of the fifth element OR 42, and the other two inputs 000IR additional elements OR 4 and 42 are connected to the direct and inverse outputs of the main RS flip-flop 17 and the outputs of the OR elements 41 and 42 are connected to the inputs of the seventh AND-36 element, the output of the inverter 22 is connected to the other input of the sixth element AND-NO 35 connected Vimoho m with input of the sixth element And 39, another input of which is connected to the output of the first element AND-NOT 29 and with the input of the fifth element And 38, the output of the third element AND-NOT 31 is connected to another input of the fourth element And 37, and another input of the fifth element AND 38 is connected to the inverse output of the main RS-flip-flop 17 of the opposite channel, the inputs of the base installation 0

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17 and auxiliary 1st RS-flip-flops are connected to the outputs of the fourth element And 37 and the seventh element 36, respectively, the reset inputs - with the outputs of the sixth 39 and fifth 38 elements I.

The DC motor (Fig. 2) contains a DC motor 43 and a reversible thyristor converter 44 connected to its core, series-connected speed controller and motor current regulators 45, 46 connected to the corresponding inputs of the latter sensors 47, 48 motor current, logic switching device (LPU) 49, inputs 4 and 5 of which are connected to the driver input and output of the speed controller 45, and input 6 to the output of the current sensor 48 (DT), serially connected input devices (WU) 50 and 51, phase shifter device (FSU) 52 and 53, pulse shapers 54 and 55 (PI), output stages (VK) 56 and 57, with the control inputs of the FSU 52 and 53 connected to outputs 19 and 20 of the LPU 49 respectively , and the input of the controlling voltage {and - with the output of current regulator 46, the inputs of WU 50 and 51 are connected to the power supply network, and the outputs of VK 56 and 57 - with control electrodes of the reverse thyristor converter 44.

The device works as follows.

In the initial state of the electric drive, in accordance with the signals of the reference, mismatch and load current at the inputs 4-6 of the two-threshold comparators 1 and 2 and the zero-organ 3 at the outputs of the latter, the signals XI-X5 are set at the level of logic O. The control channels 15 and 16 with This ensures the zero state of the direct outputs of the main 17 and auxiliary 18 RS-flip-flops (У1, У2, Z,, Z), which prohibits the passage of unlocking pulses from the outputs of the FSU 52 and 53 to both groups of the thyristor converter 44. When a signal arrives and positive polarity a master input controller 45 on input 4 two-threshold comparator 1 levels signa.pov XI and X2 at the outputs of the latter are as respectively logical 1 and D. Simultaneously, the output of the regulator 45 is on; error signal (current setting)

Up, which is pripolit to change the state of the two-threshold comparator 2 (X4 1, X3 O). At the same time, at the output of the I-1ShR1 33 element, a high level takes place, which from the output of the element ShTI 28:, together with a high signal level, from the output of the ele; Yenta OR 26 (Y, q 1) affects the AND-NE 31 element. A low level from the output of the latter puts the AND 37 element into the logical O state and turns on the main RS flip-flop 17 (U1 1). The change in the input signals of the elements AND-NOT 10-12, And 13 inverters 8, 9, the former 7 pauses, as well as the elements OR 27 and AND-NOT 29 (start and motor mode) does not change the signals T

XI X4 X5 Y ,. . „Y

ъ

MP

where XI, X2 are the task signals,

ХЗ, Х4 - mismatch signals - ХЗ - current signal-,

. Y, n.

Y are the signals at the outputs of the And 23, OR 28 and AND-NOT 29 elements, respectively, which determine the moments of switching on and switching on and off of the channel 15 of the health care facilities;

T is the pause signal Y1, Y2,

, Z is the signal of direct outputs of the main and auxiliary RS-flip-flops of both channels 13 and 16. When the polarization signal Up changes (transform by the current value of the motor rotation frequency from the output of sensor 47 of the reference signal U. due to disturbances from the load) the polarity of the control signal is changed from the output of current regulator 46. The pulses of the FSU 52 of the working set of the converter 44 are shifted to the zone of the inverter, and the pulses of the FSU 53 to the zone of the rectifier. There is a fall in the load current (fig.Z). When the signal Up reaches the threshold of operation, the switching of the two-threshold comparator 2 (X3 1, X4 O, Fig. 4),

 w 10 t 1), which maintains the on state of the main short-circuit trigger 17.

The high output level 19 of the LPU 49 acts on the FSU 32, which allows the generation of trigger pulses for the corresponding group 44.1 of the converter 44. Thus, the motor mode of the electric drive takes place, and the signal Uj from the output of DT 48 (the current load current) arrives at the input 6 of the zero-body 3 and provides a high level of variable X5. The operation of the control channel 15 in this mode is described by the following variable values (Fig. 4):

Y

Z, T Y1 Г Х2 ХЗ Z Y2 О

(ABOUT

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about 5

0

five

which leads to the formation at the output of the element AND-NOT 29 of the shutdown signal 0 which, acting on the element 39, ensures the reset of the RS flip-flop 17 (I S,, FIG. 4). This causes the valve group to be locked. Simultaneously with the current reaching the threshold of sensitivity DT 48 (X5 0), an impulse appears at the output of the element 13 of the pause 7, a pulse that triggers the multivibrator 14, the latter generates a single impulse of a given duration defining the currentless pause out of the work group. At the end of the pause, a high level of the output signal of the multivibrator 14 is restored, which is accompanied by the appearance of logical 1 signals at the outputs of the AND 24 and OR 28 elements of channel 16 (T Y 1, Fig. 4).

Thus, the main RS-flip-flop of the specified channel is turned on, and a high level signal is set at the output of the LCP 49 (Y2 1, Fig.4). The latter ensures the generation of unlocking pulses of the FSU 53 and, consequently, the operation of another set of converter 44. The braking mode of the electric drive begins, h 1 o in a closed automatic control system (Fig. 2) leads to the elimination of the resulting raskoglonapil Up. FencpaiutH iiMriy.iiiiCOH (; 53 now also occurs in the zone of the inverter mode and the current declines begin. With the signal Up, the signal pseudo-transducer of the two-threshold comparator begins

(ХЗ 0, Х4 1), changes in the state of the elements AND 24 and OR 27, 28 and 29 of channel 16, (Y 0). The main RS-flip-flop of the given channel is reset (Y2 O, Fig. 4) and the generation of unlocking im- stops. pulses of the fsu 53, which means the locking of the valves of the brake group of the converter 44. Similarly to the considered motor mode, the reduction of the current to 0 (x5 0) is accompanied by the formation of a dead-time pause, at the end of which the RS-flip-flop 17 of channel 15 starts, the generation of pulses of the fsu 52 and there is a motor mode of operation.

In the event of a load current occurring in the reference interval of the current-free pause, with unlocked valves of the group that left the work (caused, for example, by engine seizure, and consequently, its EMF reduction), and a possible increase of this current of positive power half-waves. Intensive quenching of the current is necessary (FIG. 3). The latter is carried out by re-enabling the previously operated group of valves, which enable pulses to the considered moment (X5, T, Fig.4) are shifted to the zone of the inverter mode. Reliable. separate control in this situation can be achieved

only if the control channel of the specified valve group is turned on unambiguously. Choosing the right channel, i.e. output RS-flip-flop (and hence the group), is implemented by introducing information on the previous state of the outputs of the LPU 49, as well as the direction of rotation of the electric drive (reference), the presence of the error and the load current. In channel 15, such a signal is formed at the output of the I-PE element 34 and, when a current appears in the interval of a pause (X5 1), is set at the logic level O (X5, Y1, Y2, inrush current, FIG. 4). This signal acts on the element And 37, from the output of which the low level signal includes the main RS-flip-flop 17, released from the work of the valve group 44.1.

with

JQ (5 20

25 so

35

40

.

0

five

The start signal of the AND-NE 34 element simultaneously affects the AND-NE element 29, and thus maintains a high level of the trip signal, thereby preventing the reset of the specified trigger. The correct channel definition in this case is achieved by the signals of the two-threshold comparators and the inverse outputs of the auxiliary triggers 18 of both channels, which are fed to the inputs of the AND-NE element 34.

At the same time, the combination Х1 ХЗ 1 uniquely identifies the indicated element in channel 15, since the high level of variable XI corresponds to the specified direction of rotation (signal llj at the input of controller 45), which does not depend on external disturbances, and the high level of variable X3 setting XI 1) is possible only when the feedback signal deviates from the set reference U, which is determined by the corresponding polarity of the error signal Up and characterizes the braking mode of the drive pai-bots (XI X4 1 at and 0, Up O - motor mode, XI X 1 and when, O, brake mode). The high level state of the null organ 3 and the inverse outputs of the auxiliary RS flip-flops of both channels (X5 Z, Z 1) characterizes the interval of the pause and the moment of current surge. At the same time, the connections of the direct and inverse outputs of the main RS-flip-flops 17 of channels 15 and 16 with the corresponding inputs of the elements OR 41 and 42 maintain the required state of the auxiliary RS-flip-flops 18 of both channels Z, Z 1 for the whole time of occurrence and quenching of the current in the pause . The indicated values of the variables unambiguously determine the state of the output signals of the LPU 49 to the pause start point (at the preceding moment) and are necessary to form a turn-on signal for switching on the main RS-trigger 17 of the channel from the group's work. The absence of these signals as part of the input signals of the AND-HE element 34 does not provide an unambiguous assignment of its output signal to the pause interval, since the XI X3 X5 1 combination is possible before the pause (XI, X3, X4, X5, T, Fig. 4). ) and can be attributed to the beginning of the brake mode, which means 115

It reduces the reliability of the remote control unit separately.

Thus, the combination of variables XI X3 X5 / 1 - zt 1 uniquely identifies the element behind and channel 15 and the low level of the turn-on signal, which ensures a high level of signal Y1 iia, output 19 of the health center 49, and the operation of the thyristor group 44.1 V The presence of a combination of variables X2 X4 O, X5 Z, 1 at the inputs of the same channel I-IE of channel 16 at the input level 20 and the locked state of the thyristor group 44.2 is low.

The operation of the thyristor group 44.1 in the inverter mode is accompanied by an intense quenching of the arising current, which occurs without interrupting the pause count (Fig. 3). Upon reaching the current threshold of sensitivity of the DT 48, a null organ 3 switches (X5 O and the output of the NAND 34 element receives a high level signal which, together with the logical 1 signal from the output of the NAND 31, provides a high level of the output signal And 37 (S,, Fig. 4). At the same time, the logical 1 signal from the output of the IS-NOT element 34 and the inversion signal of the variable X5 from the output of the inverter 22 affect the IS-HE element 35, the low level of the output signal of which provides a similar the output of the element And 39 and reset the main RS-t rigger 17 of channel 15 (R, Y Y1, Fig. 4). At the end of the pause, channel 16 is turned on in the same way as described for the case of braking.

The operation of the LPU 49 when reversing the electric drive is carried out by changing the polarity of the master signal U, which leads to the switching of the two-threshold comparator 1 (X2 1, XI O), and the entry into operation of the channel 16 of the LPU 49. The work of the latter is similar to that of channel 15 LPU 49 at XI 1 X2 O.

Claims (1)

Invention Formula A device for separate control of a reversible thyristor converter, containing two two-hygrograss comparators and a zero-organ. The inputs KOTopf, ix are input p. 0 5 o .. five 0 I 2 The signals are connected to the sources (lh assignment, lgsovani and load current, respectively, pause forcing, containing two inverters, three AND-I, I element and multivibrator, and the input of the first two I-I elements, as well as input The first inverter is connected to the corresponding paraphase outputs of the second double-threshold comparator, and the output of the first inverter is connected to another input of the second AND-NOT element, the outputs of the two above-mentioned AND-NO elements are connected to the inputs of the third AND-NOT element connected to the first output The input element is And, the output of which is connected to the input of the multivibrator, and the output of the latter is connected to the input of the second inverter, and the outputs of both are paraphase formers of a pause generator, two balanced controls, 1x channels, each of which contains a main and auxiliary RS triggers, the npHMfjie outputs of the main RS-flip-flops are the device outputs, two inverters, three AND and OR elements, the AND-N element element, and an AND-OR element, the first input of the first two AND elements, the first OR element, and the AND element -Or as well the second input of the last and both inputs of the second element OR are connected to the corresponding paraphase outputs of the first two-threshold comparator, the first inputs of the third AND element and the first AND-NE element, the input of the first inverter, and the third input of the second AND element and the seventh input of the AND-OR element are connected to the corresponding paraphase outputs of the second two-threshold comparator, the second input of the first element AND-NOT and the input of the second inverter are connected to the output of the zero-organ, and the third input of the first element AND-NOT - with the output of the second element OR, The third inputs of the third element AND, the second element NAND, as well as the second and third inputs of the element AND the pause maker are connected to the corresponding direct and inverse outputs of the auxiliary RS flip-flops of both channels, the fourth input of the element And the pause maker is connected to the output of the second inverter, parafadnyh outputs of the generator pause connected to the fourth inputs of the second element AND and the element AND-OR, as well as Vos1, mt) 1m input (.- 1M subsequently, the outputs of both mentioned elements are connected to the inputs of the third OR element connected by its output to one input of the third AND-NOT element, the other input of which is connected to the code of the first OR element, the second the input of which is connected to the output of the first element AND, the second and third inputs of the last element are connected to the outputs of the first inverter and the fourth element AND-NOT, respectively, which are connected to the outputs of the second element AND-NOT and the third element AND, the other input of the second element AND-NOT connected with the output of the second inverter, and the output of the first inverter with the corresponding inputs of the AND-OR element, the second element AND, and the first element AND-NOT of the pause generator, characterized in that, in order to increase the reliability of the separate control, it is additionally entered the fifth, sixth and seventh elements AND-NOT, quarter-fifth, fifth and sixth elements AND, the third inverter, the fourth and fifth elements OR, and the first element AND-NOT provided with an additional input connected to the inputs of the fourth elements OR and And, the sixth element and not, as well - with the input of tr another inverter and output p NAND element, the first three inputs of which are connected to the corresponding outputs of both two-threshold comparators and the zero-organ, and the other two to the inverse outputs of the auxiliary RS flip-flops of both channels, the third inverter going to the input of the fifth OR element, and the other two the inputs of both additional elements OR are connected to the direct and inverse outputs of the main triggers, while the outputs of the above SHS elements are connected to the inputs of the seventh AND-NO element, the output of the second inverter is connected to another input of the sixth ele An IS-NOT connected by its output to one input of the sixth element AND, the other input of which is connected to the output of the first AND-NO element and to the input of the fifth AND element, the output of the third AND-NO element is connected to the input of the fourth AND element, and the other the input of the fifth element I is connected to the inverse output of the main RS-flip-flop of the opposite channel, the installation inputs of the main and auxiliary RS-flip-flops are connected to the outputs of the fourth element AND AND the seventh element AND-NOT respectively, the reset inputs - with the outputs of the fifth and sixth element in I.