SU1390763A1 - Thyratron motor - Google Patents

Abstract

The invention relates to electrical engineering. The aim of the invention is to ensure the stabilization of the frequency of rotation in the process of compensating voltage beats. This goal is achieved by the fact that a tachogenerator 1 1, logic elements AND 12.13, logic elements, NOT 14.15, logic elements OR 16-18, trigger 19, pulse driver 20, integrator 21 with reset, comparator 22 the storage element 23 and the inverter 24. As a result, the control pulse of the rectifier is shifted (в) 4 by an angle (5V /, decreasing the voltage B 4, if the possibility of unlocking B 4 and the inverter 2 simultaneously occurs. Lo1 to the next impulse the control is shifted by the same amount, increasing the voltage B 4. As a result, the specified voltage and rotation frequency is maintained. 2 or i (L

Description

with so about

Oi

with

The invention relates to: electrical engineering, in particular, to an electric drive and can be used to create high-speed electrical power with a wide range of load variations.

The purpose of the invention is to ensure the stabilization of the rotation frequency in the process of compensating the beating voltage of an electric motor.

Fig. „1 shows a functional diagram of a valve electric motor; t € | l; FIG. 2 shows the voltage diagrams at the output of the E1 functional units (electric motor

 The valve electric motor contains an excited synchronous machine 1S of the root winding of which is connected through a series-connected equalized inverter 2, smoothing dG1assel 3 and control of rectifier 4 to an alternating current source, the sensor 5 of the rotor position of the synchronous machine 1, the output of which is connected to the system input 6 inverter controls, a beating compensation unit 7 connected in series, an adder 8 and a rectifier control system 9 4 "A second input from the mapper 8 is connected to a rotational speed sensor 10 about Kpoivie, the motor contains a tag generator 11, two logical elements AND 12 and 13, two logical elements NOT 4 and 15, three logical elements OR 16 18, trigger 19, driver 20 pulses, integrator 21 matching, comparator 22, remembered element 23 inverting amplifier 24,

The output of the inverter control system 6 is connected to the input of the first element OR 16, the output of which is connected to the first input 1 Trigger 19, the output of which is connected to the input of the first element NOT 14, to the first control input of the beat compensation unit 7, and to the input of the pulse former 20, the output of which is connected to the first input of the first element AND 12, the output of which is connected to the first input Storage of the storage element 23 and through the second element EE 15 to the first, the input of the second element AND 13 The output of the element 13 and is connected to the second input o- M1 "1ayuschego member 23, and the second input with BTOpbiM input of the first AND gate 12 and the output of second OR

3907632

17, the inputs of which are connected to the output of the rectifier control system 0. The output of the first element NOT 14 is connected to the first input of the third element OR 18, the second input of which is connected to the second input Reset trigger 19 and the output of the comparator 22, and the output to the second input Reset

1Q of integrator 21 with reset The output of integrator 21 is connected to the input of comparator 22, and the input is connected to tachogenerator 11 and the second input of beat beat compensation unit 7, the output of which through an inverting amplifier 24 is connected to the third input of the storage element 23, whose output is connected to the third input of the adder 8 The valve electric motor works as follows

In the time interval, the control pulses of the inverter 2 at the output of the inverter control system 6 are summed by the element OR 16 (FIG. 2a)

25 and arrive at the first start input of the trigger 19, which is transferred to the logical 1 (fygo2b) state and through the elements NOT 14 and OR 18 removes the signal from the input. Resetting the integrator 21 "A ramp signal is generated at the output of the integrator 21 (figv), the tempo the buildup of which is directly proportional to the frequency of rotation of the valve motor. In addition, the trigger 19 of the logical 1 connects the beat compensation unit 7, at the output of which an analog signal is generated and proportional to the frequency of rotation, which is summed

40 C. I with a setpoint signal U rotation frequency in the adder 8, When the linear signal of the interleaver 2 reaches the threshold of the comparator 22, the output of the comparator 22 (Fig 2p) is generated at the output of the second input Reset trigger 19 and translates it into. Under the action of the cutoff of the output signal of the trigger 19, the pulse shaper 20 generates a pulse and,; р (Fig.2d), the length of the torus is equal to the duration of the control pulses of the control system 9

35

50

55

by the rectifier, and the beat compensation unit 7 is turned off. The signal at the output of the adder 8 and 7 (Fig. 2e) takes a predetermined value. With a predetermined control angle, control more pulses are generated at

by the rectifier, and the beat compensation unit 7 is turned off. The signal at the output of the adder 8 and 7 (Fig. 2e) takes a predetermined value. With a predetermined control angle, control more pulses are generated at

the output of the rectifier control system 9 (Fig. 2g) with the filling element 23 does not participate in the operation

At time moment tg, the pulses of the imaging unit 2 and the element OR 17 coincide, and a pulse (fig, 2i) is formed at the output of the element 3 and the element 23 goes into the information storage state. Under these conditions, the output of the storage element 23 using an inverter 24, an analog signal is formed that is equal in magnitude & opposite in sign and is fed to the third input of the adder 8 As a result, the angle of the rectifier control at time tj is about 5 + Lo /, and at time point; tj o / o ( l4 where ofj is the angle corresponding to the voltage h Dani U. A reset from the storage element 23 (, 3) is carried out at the moment of time t by the control pulse of the rectifier through the elements OR 17 and I 12 (FIG. 2) To turn on the thyristors of the mitels at the moment of time would lead to to a throw: current (moment) and a change in the rotation frequency due to the difference in the instantaneous values of the voltage of the rectifier uJ (t) (figo2m) and the counter-emf of the motor Eoi, (t) (figo2l),

Thus, the proposed device allows to reduce the difference between the rectifier voltage Uo / 4 (t) and the counter-emf Ecij (t) and decrease. current inrush, maintain the mean operating voltage of the rectifier specified during the period, which increases the stabilization of the frequency of rotation of the valve motor

Claims (1)

Invention Formula A valve motor containing a synchronous machine, the root winding of which is connected through a series-connected controlled inverter, smoothing the choke to the AC source, a rotor position sensor, the output of which is connected to the input of the inverter control system, is connected in series Q 0 5 Q 0 five 0 The beating compensation unit, the adder and the rectifier control system, the second input of the adder are connected to the unit of rotational speed, characterized in that, in order to ensure the stabilization of the rotational frequency in the process of beat sensation, two a logical element NOT, three logical elements OR, a trigger, a pulse shaper, an integrator with a reset, a comparator, a memory element and an inverting amplifier, the output of the inverter control system connected to the inputs OR, whose output is connected to the first input. Trigger start, the output of which is connected to the input of the first logical element, NOT, the first control input of the beat compensation unit, and the input of the pulse former, the output of which is connected connected to the first input Storage of the storage element and through the second logical element NOT, to the first input of the second logical element AND, the output of which is connected to the second input Reset of the storage element a, and the second input of the second logic element AND is connected to the second input of the first element AND, and with the output of the second logical element OR, whose inputs are connected to - the output of the rectifier control system, the output of the first logical element is NOT connected to the first input of the third logical element OR, the second the input of which is connected to the second input Reset trigger and the output of the comparator, and the output is connected to the second input Reset of the integrator with a reset, the output of which is connected to the input of the comparator, and the input - to the tachogenerator and the second input Lok compensation: beats whose output through the inverting amplifier is connected to the third input of the memory element whose output is connected to the third input of the adder