SU1667214A1 - Device forstabilization of rotational speed of motor - Google Patents

Abstract

The invention relates to electrical engineering and can be used to stabilize the rotational speed of an electric motor in automatic control systems. The purpose of the invention is to increase speed. The device additionally contains two pulse counters 18 and 19, which set the converter 17 to COD-PWM in the state corresponding to the minimum or maximum rotational speed of the engine 18, depending on the ratio of the reference and rotation frequencies. In the stabilization mode at comparable values of the required and actual frequencies, the counters do not affect the operation of the device. 2 Il.

Description

one

The invention relates to electrical engineering and can be used to stabilize the rotational speed of an electric motor in automatic control systems.

The aim of the invention is to improve the speed

Fig 1 shows the functional diagram of the proposed car in Fig 2 structural diagram of the converter PWM CODE

The device contains a series of highly connected speed setting 1 and a driver setting 2 of the setting parameter to frequency generator 3 reference frequency pulse speed sensor 4 The first generator output 3 reference frequency is connected to the clock inputs of the first and second counters 5 b pulses and the second output - with frequency divider 7 The first by-course frequency divider 7 is connected to clock

the first and second inputs of the counters are 8 9, and the second output with the input of the element 2IMI HF 10 whose first input is connected to the second output of the comparator 11

The first output of the comparator 11 is connected to the input. Choice of the counting direction of the reversible counter 12 The first and second groups of inputs of the comparator 11 are connected respectively to the outputs of the first and second registers 13 and 14, the inputs of which are connected to the outputs of the first and second totalizing counters 8.9, the Reset inputs which are connected to the second outputs, respectively, of the first and second pulse counters 56 Inputs Resolution of the counting of totalizers 8.9 through inverters 15 16 connected to the third outputs and inputs Resolution billing accounts

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5,6, the first outputs of each of which are connected to the corresponding clock inputs of registers 13, 14, and the Reset inputs 5,6 are connected respectively to the outputs of the converter 2 of the driving parameter to the frequency and the pulse 4 speed sensor. The output of element 2IL- NOT 10 is connected to the clock input of the reversible counter 12, the information outputs of which are connected to the information inputs of the COD-ShIM converter 17, the output of which is the output of the device.

In addition, the device contains the third and fourth pulse counters 18,19 and the third inverter 20. The converter 19 COD-PWM is additionally equipped with two inputs. Output Transfer of the reversible counter 12 and its input. Resolution of the account is connected via the third inverter 20. The clock input of the third counter 18 and the Reset input of the fourth counter 19 are combined and connected to the output of the pulse 4 speed sensor. Input Reset the third counter 18 and the clock input of the fourth counter 19 are combined and connected to the output of the converter 2 of the driving parameter to the frequency. The first input of the 17 COD-PWM converter is connected to the output and the input of the third counter 18 counting, the second input of the 17 COD-PWM converter is connected to the output and the input of the fourth counter 19 counting converter, the 17 COD-PWM converter consists of the subtracting counter 21, the clock generator 22 pulses, elements NOT 23,24, element 2I 25, elements 2ILI 26.27, RS-flip-flop 28, element NO 29.

The device works as follows.

An input signal equal to or proportional to the frequency of rotation of the electric motor is fed to the input of the converter 2 of the driving parameter to the frequency from the setpoint 1 of speed. The converter 2 of the driving parameter converts the input signal into a continuous sequence of pulses with a frequency Psad proportional to the frequency of the specified frequency. The value of the actual frequency of rotation of the motor is removed from the pulse sensor 4 speed in the form of a sequence of pulses with a frequency Po, proportional to the instantaneous speed. When the device is turned on, the output of the converter 2 of the driving parameter to the frequency of the input of the Reset of the first counter of 5 pulses receives pulses of a given frequency. The same pulses go to the Reset input and the clock input of the third and

fourth counters 18 and 19 pulses. The clock input of the third counter 18 pulses and the input Reset the fourth counter 19 pulses connected to the output of the sensor 4

speed. If three impulses come from the converter 2 of the drive parameter to the frequency, and not a single pulse from the speed sensor 4 during this time, then the output of the fourth pulse counter 19 is set to 1, which blocks the counting of the pulses received at its input clock input The resolution of the account and at the same time sets the converter 17 COD-PWM to the state O

5 which corresponds to the maximum engine speed. The engine with the highest possible acceleration begins to gain frequency. As soon as the engine speed is comparable to the set,

0 to the inputs Reset and clock of the fourth counter 19 pulses will come in turns pulses, and the pulse at the input Reset will continuously zero the counter, so the logical O level will be constantly at the input. Counter 19 will not affect the operation devices that are in the frequency stabilization mode at comparable values of the specified and actual frequencies. Similarly, the third pulse counter 18 is designed to form the operation of the device when the actual frequency is significantly higher than the set one. In this case, the arrival of three

5 pulses from the speed sensor 4 per clock input of the third counter 18 pulses and the absence of pulses at the input during this time interval. Reset log.1 level is set at its output blocking

0 clock input at the Resolution input, stopping further counting and at the same time setting the 17 COD-PWM converter to the log state, 1, which corresponds to dynamic braking with maximum acceleration. In the stabilization mode with compared values of the required and actual frequencies, the output of the counter is 18 -log, O, and the counter does not affect the operation of the device.

0 In the stabilization mode, the device operates as follows.

From the output of the converter 2 of the driving parameter to the frequency to the input. Reset of the first counter 5 pulses go to them 5 pulses of the given frequency. The first pulse zeroed the pulse counter 5, which starts counting the pulses arriving at its clock input from the pulse generator 3. The frequency of the pulse generator 3 may be as high as possible for a given

chip type On the first pulse received at the first clock input of the pulse counter 5, the level of logic 1 appears at its first output, and the information from the first summing counter 8 is recorded into the first register 13. After the first pulse arrives from the converter 2 at the input The counter 5 pulses on its third output sets the level of the log. O, and the output of the first inverter 15 sets the level of the log. H, therefore, no information fails while writing to the register. According to the second pulse from the pulse generator 3, received at the clock input, the first pulse counter 5 is set to a state in which the level / sub 1 is observed at its second output, the first summing counter 8 is reset. By the third toner pulse of the Jurassic 3 pulses the level is T / stanavs ps1c at the third output of the counter 5 ko.reshsh pod with input Resolution of the counter of the first counter 5 pulses, prohibiting further passage of the tag pulses / lis but the counter, and at the same time the inverter 15 signal log.O allows the sc account 8 gchiku frequency value output from the first frequency divider 7, arriving at the clock inputs of the first and E a m p of about i totalisers 8 and 9 is determined by varying the drive signal range. At the minimum setting signal, the first summing counter 8 must count to the state in which the level of logic 1 is set at all its outputs. Upon the arrival of the second pulse from the converter 2, the first counter of impulses 5 is reset, the summing counter 8 stops, to the pulse from the generator of the pulses of the pulses, the recording of the values of the counter 8 to the register 15 is proportional to the duration of the period of the pulses Tzad of the converter 2. Similarly, the conversion of the period Tds of the frequency coming from sensor 4 speed digital code, which is recorded on register 14. Digital comparator 11 continuously compares digital codes received from registers 13 and 14 If digital register code 13 is greater than register code 14, ie, the period TzdDs, at the first output of the comparator 11 is the signal of the logic signal. , reversible counter 12 works on subtraction, reducing its value. The clock frequency of the reverse clock 12 is determined by the range of change of the driving signal. The signal from the output of the counter 12 is supplied to the converter 17 of the COD-CHIM converter, which controls the operation of the engine and

reduces its frequency. As soon as the value Tzad and Tds become equal, the signal log.1 appears at the second output of the comparator 11 and prohibits the passage of clock pulses to the clock input of the reversible counter 12, since at the output of element 2IL- NOT 10, a signal log.0 is set. When Tzad Tds on the first output of the comparator 11 signal log. T1, which is fed to the input

5 Select the counting direction of the reversible counter 12, increasing its value. Converter 17 COD-PWM increases the frequency of the engine. As soon as T3ad Tds, the counting by the logical loop from the output of element 2OR-NOT 10 occurs, Inverter 20 is designed to stop the reversible counter 12 when it is operating in the summation mode and there is a log on all its outputs. 1, or when it operates in the subtraction mode and the O log is present on all its outputs. Otherwise, the counter can go from the state with the maximum output code to the state with the minimum output code or vice versa, which is unacceptable

5 device operation.

Stopping is as follows.

When the reversible counter 2 is operating in the summation mode with all

0 units at its output at the output of Transfer A level log occurs. O, which through the inverter log, 1 prohibits the account on the input Account Resolution.

Similarly, when working on

5 subtraction and the presence of all zeros at the outputs of the log, O occurs at the output of the Transfer and blocks further account

Converter 17 CODE PWM works as follows

0 When a signal is received log.1 on

input 2 through the element 2ILI 27 RS-trigger 28 is set to the state log.1 and at the output of the inverter - the signal log.O corresponding to the engine spin-up. Log.1 to

5, the first input through element 2ILI 26 sets the RS flip-flop to the zero state, and the output of the inverter is log.1. corresponding to dynamic braking.

With a log, O on the first and second inputs

0 from the first generator output 22 clock pulses of the PWM frequency pulse through element 2 and 25, element 2 OR 27 sets the RS flip-flop to one and records the code received at the inputs

5 preset 1, .. t subtractive counter 21, a pulse at its input PE. At the end of the recording, the counter begins to subtract the pulses arriving at its clock input. When fully zeroed, the output of the CO transfer of this counter results in a log.0 level.

which, through the inverter 24 and element 2ILI, sets the RS flip-flop to the zero state, completing the formation of an impulse proportional to the code on the preset inputs of the subtracting counter. As a trigger 28, an RS-trigger is used with a priority on the S-input in order to force it to set the pulse in the PWM frequency to log.1, since the state at its R input may be undefined at the moment after the end of the formation of the next pulse. The element NOT 23 blocks the passage of the pulse frequency PWM through the element 2 and 25 in the presence of log.G on the first input.

Thus, the device provides an increase in the speed of stabilization of the frequency of rotation of the electric motor due to the fact that, with large differences in the required and actual frequencies of rotation, the formation of a decrease in the error with maximum acceleration is ensured.

Claims (1)

Apparatus of the Invention A device for stabilizing the rotational speed of an electric motor, comprising a serially connected speed controller and a driver for setting a frequency, a reference frequency generator, a pulse speed sensor, the first output of the reference frequency generator is connected to the clock inputs of the first and second pulse counters, the second output is connected to a frequency divider , the first output of which is connected to the clock inputs of the first and second summing meters, the second output is connected to the second input ale nta 2ILI-NOT, the first input of which is connected to the second output of the comparator, the first output of which is connected to the input. Selecting the counting direction of the reversible counter, the first and second groups of inputs of the comparator are connected respectively to the outputs of the first and second registers, the information inputs of which are connected to the outputs of the first and second respectively the second summing counters, the inputs of the Reset of which are connected to the second outputs of the first and second pulse counters respectively, and the inputs of the counting through the first and second inverters Linked to the third outputs and inputs pulse counters, the first outputs of each of which are connected to the corresponding clock inputs of the registers, and the Reset inputs are connected respectively to the outputs of the converter of the driving parameter to the frequency and the pulse speed sensor, the output of element 2IL is NOT connected to the clock input of the reversible counter, the information outputs of which are connected to information entrances the COD-PWM converter, the output of which is the output of the device, is so that, in order to improve speed, the third and fourth pulse counters are introduced from it, the third inverter and the COD-PWM converter are equipped with two additional inputs, output Transfer reversible counter and its input Resolution resolution connected via a third inverter, clock input of the third pulse counter and input Reset the fourth pulse counter combined and connected to the output of the pulse speed sensor, input Reset the third account The pulse pulse and the clock input of the fourth pulse counter are combined and connected to the output of the converter of the driving parameter to the frequency, the first input of the CODE-PWM converter is connected to the output and the input of the counting resolution of the third counter pulse, the second input of the COD-PWM converter is connected to the fourth output pulse counter. “IS - sisH il Bx.l about- 22 25 26 28 29 27