SU1725190A1 - Voltage controller - Google Patents

Abstract

The invention relates to measuring and computing technology and can be used in computerized systems for controlling parameters using a computer. The purpose of the invention is to increase the speed and reliability of the control. The device contains a comparator, a generator of linearly varying voltage, D- triggers and comparison schemes for the lower and upper limits, the first and second elements OR, the first and second elements AND, the element NOT, the delay element, the trigger overload, the trigger reverse, the read resolution trigger and a voltage code storage register. The purpose of the invention is achieved by excluding the time of measuring operations after achieving equal controlled and reference voltages. 1 il. “Yo

Description

The invention relates to measuring and computing techniques and can be used in automated systems for controlling parameters using computers.

A device for comparing signals is known comprising a control unit, a linear voltage generator, a pulse generator, comparators, a key, and a trigger.

It is also known a voltage monitoring device comprising a comparator, a linear voltage generator, two comparison units, three triggers, three AND elements, two OR elements.

These devices have low speed, since when a linear voltage generator changes, it generates a voltage in the range from zero to maximum.

The closest in technical essence to the present invention is a voltage monitoring device comprising a comparator connected to the first input of the device, a second input to the analog output of the generator of linearly varying voltage, the first and second coincidence elements connected by the first inputs to the vector and the third, respectively. the device inputs, the second inputs with digital outputs of the generator of linearly varying voltage, and the outputs, respectively, with the input of the second D-flip-flop, and the RS-flip-flop, the output of the comparator connected to the D-inputs of the first and second D-flip-flops, the outputs of the first and second elements are connected respectively to the coincidence S- and R-inputs of RS-trigger whose output is connected to the control input of the oscillator linearly varying voltage VI

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The direct output of the first D-flip-flop is connected to the first output of the device and the S-input of the second D-flip-flop connected by an inverse output to the R-input of the first D-flip-flop and the second output of the device.

A disadvantage of the known device is the low reliability of the measurement due to the low speed and low information content, the dependence of the control accuracy on the tolerance range, which does not allow its use in automated control systems.

Low speed due to the following.

In each measurement cycle, the voltage of the reference voltage applied to the input of the comparator varies within the allowable values for the measured voltage. It varies from the lower acceptable level to the upper or from the upper to the lower.

The value of the measured voltage is between the upper and lower voltage levels. Therefore, the reference voltage will change (for example, in the case of a cycle with an increase in the reference voltage, it will increase) and after that the comparator will determine the equality of the reference and measured voltages. Consequently, the fact of fixing the equality of voltages (switching the comparator to the state of logical G or logical O) during the time when the voltage varies from one limit voltage to another occurs once during the time corresponding to one state of the pulse generator of the linearly varying voltage .

During the time preceding the fact of fixing the equality of controlled and reference voltages and the time after fixing the fact of their equality, prior to recording the measurement results (comparator state), the output triggers controlling the device nodes do not change their state.

At this time, voltage monitoring is not performed.

At the same time, the state of the comparator is fixed (recorded in the flip-flops) with the values of the pulse counter of the generator of a linearly varying voltage corresponding to the specified limit voltages.

The wider the tolerance range of the measured voltage, the lower the speed of the device.

In addition, the device does not provide the output value of the measured voltage,

which does not allow to conduct diagnostics and control of parameters using a computer.

The purpose of the invention is to increase the speed of the device and the reliability of the control.

The goal is achieved in that a device containing a comparator, a linearly varying voltage generator, including a series-connected pulse driver, a reversible counter and a digital-analog converter, lower and upper limits D-flip-flops, in which the information input of the device is connected to the first input of the comparator, the second input of which is connected to the output of the digital-to-analog converter of the generator of linearly varying voltage, the output of the reversible counter of which is connected to the first in by the moves of the lower and upper limits comparison circuits, the input of setting the lower limit code of the device is connected to the second input of the lower limit comparing circuit, the output of which is connected to the information input of the D-trigger of the lower limit, the output of which is the output of the signal Less than a device, the input of setting the code of the upper limit of the device connected to the second input of the upper limit comparison circuit, the output of which is connected to the information input of the upper limit D-flip-flop, the output of which is the output of the signal More device, is entered the first and second elements OR, the first and second elements AND, the element NOT, the delay element, the overload trigger, the reverse trigger, the read enable trigger and the voltage code storage register, and the comparator output is connected to the first input of the first OR element whose output is connected to the information the input of the trigger trigger, the output of which is connected to the control input of the reverse of the reversible counter of the generator of linearly varying voltage, the output of the pulse shaper of which is connected to the first inputs of the first and second elements And the input element is NOT, the output of which is connected to the input of the delay element, the output of which is connected to the recording control inputs of the reverse trigger, the overload trigger, the upper and lower limits D-flip-flops and the voltage code storage register, the information input of which is connected to the generator's reverse counter output linearly varying voltage, and the output is the output of the voltage code of the device, the output of the overload signal of which is connected to the output of the overload trigger and the second input of the first element And, the output

which is the output of the readout signal of the device, the output of the comparator is connected to the second input of the second element I, the output of which is connected to the installation input of the read resolution trigger unit whose output is connected to the third input of the first element I, the output of the overflow signal of the reversible generator of the linearly varying voltage is connected to the first input of the second OR element, the output of which is connected to the installation input of the overflow trigger unit, the installation input of which is connected to the output from the borrowing signal of the reversible generator of a linearly varying voltage, and the output of the overflow trigger is connected to the second input of the first OR element and the information input of the overload trigger, the device start input is connected to the installation inputs of the reverse voltage generator of the alternating voltage trigger, trigger reverse, overload trigger, upper and lower limit D-flip-flops, read enable trigger and the second input of the second OR element.

The drawing shows a functional diagram of a voltage monitoring device.

The device contains a generator of linearly varying voltage, a comparator 2, schemes 3 and 4 comparing the upper and lower limits, D-flip-flops 5 and 6 upper limit, lower limit, overload trigger 7, reverse trigger 8, overflow trigger 9, resolution trigger 10 reading, delay element 11, first and second elements AND 12 and 13, first and second elements OR 14 and 15.17 of the signal More, output 16 of the signal Less, output element NO 18, register 19 for storing the voltage code.

The linearly varying voltage generator contains a pulse shaper 20, a reversible counter 21, and a digital-to-analog converter 22 (D / A converter).

The device has information input 23, start input 24, upper limit code input 25, lower limit code input 26, read enable signal output 27, overload signal output 28, voltage code output 29.

In the device, information input 23 is connected to the first input of the comparator 2, the second input of which is connected to the output of the DAC 22 of the generator 1 of a linearly varying voltage, the output of the reversible counter 21 of which is connected to the first inputs of circuits 3 and 4 comparing the upper and

the lower limits, the input 26 of setting the code of the lower limit of the device is connected to the second input of the lower comparison circuit 4, the output of which is connected to the information input of the lower limit P-trigger 6, the output of which is the output 16 of the signal Less than the device, the input 25 of setting the code of the upper limit of the device connected to the second input of circuit 3 compared to the upper limit, the output of which is connected to the information input of the 6-flip-flop 5 of the upper limit, the output of which is the output 17 of the signal More device, the output of the comparator 2 is connected with the first

5 by the input of the first element OR 14, the output of which is connected to the control input of the reversal of the reversing counter 21 of the generator 1 of linearly varying voltage, the output of the pulse former 20 of which

0 is connected to the first inputs of the first and second elements 12 and 13 and the input of the HE element 18, the output of which is connected to the input of the delay element 11, the output of which is connected to the recording control inputs of trigger 5 reverse 8, overload trigger 7, D-flip-flops 5 and 6 upper and lower limits and register 19 of the voltage code storage, the information input of which is connected to the output of the reversible counter

0 21 generators of linearly varying voltage, and the output is the output 29 of the voltage code of the device, the output 28 of the overload signal of which is connected to the output of the overload trigger 7 and the second input of the first element AND 12, the output of which is the output 27 of the read resolution of the device , the output of comparator 2 is connected to the second input of the second element And 13, the output of which is connected to the input

0 installation per unit trigger resolution 10 reading, the output of which is connected to the third input of the first element AND 12, the output of the overflow signal of the reversible counter 21 of the generator 1 linearly varying 55 voltage is connected to the first input of the second element OR 15, the output of which is connected to the installation input to an overflow trigger 9, whose zero input is connected to an output

0 of the signal of the reversible counter of the generator 1 linearly varying voltage, and the output of the overflow trigger 9 is connected to the second input of the First element OR 14 and the information input of the overload trigger 7, the start input 24 of the device is connected to the inputs of the installation of the reversible counter 21 of the generator 1 linearly changing voltage, trigger 8 reverse, trigger 7 overload, D-trigger 5 and 6 upper and lower limits, trigger 10 resolution reading and the second input of the second element OR.

The device works as follows.

In the initial state of the device, the signal at the input 24 of the start of operation sets the trigger resolution trigger 10, readout O, triggers 5 and b, triggers 7 and 8, reversible counter generator 21 of the linearly varying voltage through the reset inputs and trigger 9 overflow, passage through the second element OR 15.

At the input of the reverse reverse counter 21 pulses, the reverse signal is missing.

The pulses fed to the reversible counter 21 pulses from the output of the pulse former 20 do not change its state.

In the initial state, at the outputs 28, 17, 16 and 27 of the overload, the signal is larger, the signal is smaller, the data reading resolution is logical o. At the output 29 of the voltage code there is arbitrary information.

Information input 23 provides a supply of measured voltage to the device.

The logical 1 signal at the input 28 of the overload signal appears when the measured voltage goes beyond the limits of the device measurement.

A logical 1 signal at the output 17 of the signal More and an output 16 Less appears when the measured voltage exceeds the admissible range of voltages specified by the input codes of the device when the measured voltage is exceeded or under- measured, respectively.

The synchronization pulses at the data readout output 27 confirm the accuracy of the information at the device outputs and provide for the reading of information from the device in the computer, eliminating the reading of false information when it is changed at the device outputs.

Before starting the measurement, the codes corresponding to the upper and lower limits of the measured voltage are set at the upper and lower limits of inputs 25 and 26, at which the device should issue a message (a logic level 1 signal) at the output 17 of the Greater signal or the output 16 Less. A monitored voltage is applied to information input 23. The operation of the device begins by removing the device setup signal from the start of operation input 24.

A reversible pulse counter 21 starts counting pulses arriving at its input from a generator of 20 pulses. Code on

the output of the reversible pulse counter 21 is successively increased (direct count).

The digital code of the reversible counter 21 of pulses controls the bits of the D / A converter 22, and a voltage stepwise increasing in amplitude is formed at its output.

This voltage is applied as a reference to the input of the comparator 2. The second input of the comparator 2 receives a monitored voltage from the information input 23. At the input of the comparator 2, the signal changes its logical level as it passes through the equality of voltages.

The value of the digital code at the time of equality of the voltages corresponds to the voltage being measured and is determined by the formula.

".- $

NX

where and is the value of the reference voltage of the DAC 22;

n - the number of bits of the reversible counter 20 pulses;

2 - the capacity of the reversive counter 21 pulses;

NX is the counter code corresponding to the number of pulses arriving at the moment of equality of pulses at its input.

When passing through the equality of stresses, when the reference voltage becomes greater than the measured one, the level of the logical G is set at the output of the comparator.

At the end of the next counting pulse, a signal appears at the output of the pulse former 20 at the output of the element HE 18, according to which the delay element 11 generates a pulse delayed relative to the counting pulse.

On the leading edge of this signal, arriving at the C input of the trigger 8 for the reverse, the current state and the signal from the output of the comparator 2 are recorded in the trigger 8 for the reverse through the first element OR 17.

In the event of a rise in the reference voltage, until a voltage is equal, the reverse trigger will record (or confirm) the logical O signal and the reversible pulse counter 21 will increase its code, continuing the forward counting and, accordingly, the reference voltage will increase.

By the appearance of the logical level T at the output of the comparator 2, the trigger 1 of the reverse 8 will be written as logical 1, i.e. at the output of the trigger trigger on Wits reverse signal. This signal is fed to the input of the reversible counter of pulses 20, which goes into the countdown mode. On the next counting pulse, the code at the output of the reversible counter 21 pulses will decrease by one. Accordingly, the reference voltage decreases.

If during this time the measured voltage has not changed, then a transition will occur through the equality of the stresses from the excess of the reference voltage over the measured one to the excess of the measured voltage over the reference one. At the output of the comparator, the state of logical O is set, and the reverse command from the output of the reverse trigger 8 is removed. The reversible pulse counter 21 goes back into direct counting mode and continues the process similar to that described.

Thus, if the measured voltage does not change its magnitude, then the reference voltage, after the start of the measurement, will reach a value equal to the magnitude of the measured voltage, the next counting pulse will be less than the standard voltage measured by one step the next counting pulse will again be equal to the measured one, then again decrease by one step, and so on. Consequently, the measurement process lasts only two periods of counting pulses.

If the measured voltage while the reversible counter 21 pulses is in the reverse mode has increased, then, going into the direct counting mode, the reversing counter 21 of the pulses will have to count not one pulse, but the number of pulses corresponding to the voltage over the previous measured value of voltage.

If the measured voltage decreases when the reversible counter 21 goes into the reverse mode, then with a decrease in the code of the reversible counter 21 pulses, the equality of the voltages does not come immediately. As long as the reference voltage exceeds the measured one, the state of the logical G is saved at the output of the comparator and the signal of the reverse is confirmed by the pulse at the C input of the reverse trigger 8. A reversible pulse counter 21 will subtract the number of pulses corresponding to the value of the decrease in the measured voltage until it passes again through the equality of voltages and the reversible counter 21 pulses go to the direct account.

Therefore, the reversible pulse counter 21 keeps track of the value of the monitored voltage all the time.

If the value of the monitored voltage exceeds the permissible for the device (determined by the number of counter bits), then in the forward stroke mode, the reversible pulse counter 21 is completely filled, and at the output of the comparator 2, the logical level G and, accordingly, the signal does not appear. reverse The next pulse arriving at the input of the counter will cause its overflow. The value of the code in the counter will be zero, and the pulse from the overflow output of the reversible counter 21 pulses will set the state to logical one. Overflow trigger 9. The signal from its output, having passed through the first element OR 14, will be written into the trigger 8 of the reverse and will form the reverse signal.

The next counting pulse at the output of the reversible pulse counter 21 generates a loan signal and the reversible pulse counter 21 is filled to its full capacity, i.e. the previous state is restored.

By the loan signal, the overflow trigger 9 is reset, and the logical trigger O is written to the reverse trigger 8. The reverse signal is removed. As long as the value of the measured voltage will remain its value, the previous process will be repeated.

If during the next installation of the reversible counter 21 pulses on the maximum code, the input voltage turns out to be equal to or less than the reference voltage, then at the output of the comparator 2 a logical 1 signal will appear, a reverse signal will be generated and the code in the reversible counter 21 pulses will decrease and continue work on voltage measurement.

Information on the device output buses is generated as follows.

After the start of work on the first occurrence of equality of the reference and measured voltages, the signal from the second element I 13 is set to the logical 1 trigger of read resolution 10, which, in the absence of an overload signal, allows the counting pulses to pass to the output bus 27 of read data.

The code of the reversible counter 21 pulses in the pause between the counting pulses is written into the voltage code storage register 19 and outputted to the code output 29

tension The reversible pulse counter code is fed to the upper limit comparison circuit 3 and the lower limit comparison circuit A, to which the codes of the upper and lower permissible voltage levels and the corresponding input buses, respectively, arrive.

At the output of circuit 3, the comparison of the upper limit of wits signal is logical 1, if the code of the reversible counter 21 pulses exceeds the upper permissible value.

At the output of the lower limit comparison circuit 4, there will be a logical G signal if the code of the reversible counter 21 pulses is less than the code of the lower permissible voltage value.

The signals at the outputs of the comparison circuits 3 and 4 can change state during the passage of the counting pulse.

In the pause between counting pulses, they are rewritten into upper and lower limit triggers 5 and 6, respectively, associated with the output 17 of the signal More and the output 16 of the signal Less.

The output signal from the overflow trigger 9 is rewritten to the overload trigger 7 in the pause between the counting pulses.

The output signal of the overload trigger 7 prohibits the output of a data readout signal and is outputted at the overload output 28.

The time of change after the first measurement is determined by the formula

tK 2T0 + To

N2-Mi No

where tk is the time of one change;

That is the period of counting pulses;

No is the magnitude of the voltage situation;

N2 is the voltage value of the previous measurement;

NI is the magnitude of the current measurement voltage.

If the value of the measured voltage does not change over the time between two measurements, the measurement time will be two periods.

Compared with the known device, the maximum speed of the proposed device is higher by 200-300 times with higher reliability and noise immunity due to elimination of the influence of transients of the reversible counter 21 pulses.

Claims (1)

Invention Formula A voltage monitoring device containing a comparator, a linearly varying voltage generator including series-connected pulse shaper, reversible counter and digital-to-analog converter, lower and upper limit D-flip-flops, device information input connected to the first input of the comparator, the second input of which is connected to the output of a digital-to-analog converter of the generator of linearly varying voltage, the output of the reversible counter of which 0 is connected to the first inputs of the upper and lower limits comparison circuits, the input of setting the device's lower limit code is connected to the second input of the lower limit comparing circuit, the output of which is connected to the information input of the lower-level flip-flop, whose output is the output of the signal Less than the device, input setting the upper limit code of the device is connected to the second input of the comparison circuit of the upper limit, the output of which is connected to the information input 0 of the upper limit trigger, the output of which is the output of the signal Bo it bigger device, characterized in that, in order 5 speed and reliability control, it introduced the first and second elements OR, the first and second elements AND, the element NOT, the delay element, the overload trigger, the reverse trigger, the read resolution trigger and the voltage code storage register, the comparator output is connected to the first the input of the first element OR, the output of which is connected to the information input of the reverse trigger, the output of which is connected to the control input of the reverse of the reversible counter of the generator of linearly varying voltage, the output of the pulse shaper which is connected to the first inputs of the first and second elements AND and the input element NOT, the output of which is connected to the input of the delay element, the output of which is connected to the inputs of the recording control of the reverse trigger, overload trigger, D-flip-flops 5 of the upper and lower limits and the voltage code storage register, the information input of which is connected to the output of the reversible counter generator of the linearly varying voltage, and the output is 0 the output of the voltage code of the device, the output of the overload signal of which is connected to the output of the overload trigger and the second input the first element And, the output of which is the output of the signal of the reading permission of the device, the output of the comparator is connected to the second input of the second element And, the output of which is connected to the input of the installation in 1 trigger resolution reading, the output of which is connected to the third input of the first AND gate, the output signal the overflow of the reversible counter of the generator of a linearly varying voltage is connected to the first input of the second OR element, the output of which is connected to the installation input of the overflow trigger, the input of the installation of which is connected to the output of the signal of the reverse voltage generator of the reverse voltage generator, and the output of the trigger the overflow is connected to the second The first input of the IL element and the information input of the overload trigger are input, the device start input is connected to the installation inputs of a reverse voltage generator, reverse voltage trigger, overload trigger, upper and lower D trigger, second resolution trigger and second trigger inputs the inputs of the second element OR. ip