SU1645942A2 - Voltage checking device - Google Patents

Abstract

The invention relates to measuring and computing technology, the layout to be used in automated systems for controlling parameters using computers and is an improvement of the device according to the author. St. 1183943. The purpose of the invention is to increase the speed of the device. The device contains a linearly varying voltage generator, a comparator, comparison circuits, D-triggers, a recording control trigger, a delay switch element, a write pulse driver and a HE element. The stress of the device is increased by reducing the switching time from the lower to the upper permissible voltage level and vice versa. 1 il. No

Description

The device relates to measuring and computing technology, can be used in computerized systems for controlling parameters using a computer, and is optional in the author. 1183943.

The aim of the invention is to improve the speed of the device.

The drawing shows a block diagram of a device for voltage control.

The device contains a linearly varying voltage generator 1, a comparator 2, comparison circuits 3 and 4, D-triggers 5-7, write control trigger 8, delay element 9, switch 10, write pulse driver 11, element OR 12, element

NOT 13, groups of elements OR 14, groups of elements AND 15 and 16, shapers 17 and 18 of a single pulse.

The linearly variable voltage generator 1 contains a pulse former 19, a reversible counter 20, and a digital-to-analog converter 21 (D / A converter).

The drawing shows the input 22 of the measured voltage, the inputs 23 and 24 of the codes of the lower and upper levels, respectively, information outputs 25 and 26.

The device works as follows.

On power up, the triggers and the counter are set to an arbitrary state. Pulses from the former 19 pulses are fed to the input

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a reversible counter 20 pulses, with the result that the digital code at the output bits is sequentially increased or decreased.

The digital code of the reversible pulse counter 20 controls the discharge of the digits of the analog converter 21, as a result of which a voltage is generated at its output, which increases or decreases stepwise in amplitude. It is fed to the second input of the comparator 2 as a reference. At the first input of the comparator 2, a controlled voltage is applied from the first input 22 of the device. At the output of comparator 2, the signal changes its logic level as it passes through the equality of voltages. The value of the digital code at the time of voltage equality corresponds to the measured voltage Ux and is determined by the formula

Uv

Have

N

x

where U is the value of the reference voltage of the D / A converter 21;

n - the number of bits of the reversible counter 20 pulses;

2 - the capacity of the reversive counter 20 pulses;

NJ is the counter code corresponding to the number of pulses arriving at the moment of equality at its input. If the measured voltage is within the acceptable voltage (the lower level code of which is fed to the second input 23 of the device, and the upper level code to the third input 24 of the device ), and the reversible counter 20 of pulses is turned on in the forward direction, then at the moment when the voltage at the output of the linearly rising voltage generator 1 increases, compares with the controlled voltage, at the output of the comparator 2 logical level G1.

By the decay of the counting pulse entering through the element NOT 13 to the C input of the recording of trigger 7, logical 1 will be written into it. As a result, a single pulse shaper 17 will form them

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pulse, which through the element OR 12 goes to the input of the reversible counter record 20 pulses. For this pulse, the code of the upper permissible level from the third inputs through the second group of elements 15 and through the group of elements OR 14, is entered into the reversible counter of pulses. This code, coming from the output of the reversing counter of 20 pulses on the CIA 21, will increase the reference voltage to the upper permissible level, but the logical level of the signal at the output of comparator 2 does not change. At the output of the second element of coincidence, the Wits level is logical 1 due to the equality of the codes arriving at its input. By the appearance of a pulse at the output of delay element 9, the signal from the output of comparison circuit 4 will set trigger 8 to logical 1. Reversing pulse counter 20 will go into reverse mode, and the lower permissible voltage level code will be applied to the set inputs of reversing pulse counter 20. The signal from the output of the comparison circuit 4 simultaneously records from the output of the comparator 2 a signal of logic level 1 to trigger 6, with the result that the second output of the device receives a Norma signal at the upper permissible voltage level.

The following counting pulses will successively reduce the digital code of the reverse pulse counter 20 and, accordingly, the reference voltage at the input of the comparator 2. At the same time as the reference and controlled voltages at the output of the comparator 2, the logical signal O, decays the counting pulse received through the HE element 13 on the C-input of the record of the trigger 7, the logical O, will appear on it, the appearance on its forward, the output of the logical O on the inverse output will result in a logical 1 signal and a shaper 1 8 single output Pulse s will generate a pulse, which through the element OR 12 will go to the input of the record of the reversible counter 20 pulses. According to this pulse, the code of the lower permissible level from the second inputs of the device, through the first group of elements AND 15 and the group of elements OR 14 will be entered into the reversible counter of pulses. This code, received from the output of the reversing counter of 20 pulses per DAC 2), will reduce the reference voltage to the lower acceptable level. The logical level of the signal at the output of comparator 2 does not change. At the output of the first comparison circuit 3, the level of logical 1 is set due to the equality of the codes arriving at its input. By the appearance of a pulse at the output of the delay element 9, the signal from the output of the circuit 3 will set the trigger 8 to the logical state O, according to which the reversible pulse counter 20 will switch to direct counting mode, and the upper code will be fed to the installation inputs of the reversing counter 20 pulses permissible level The same signal is recorded in the first 1-trigger 5, with the result that at the first output of the device the signal is normal at the lowest acceptable level. Next, the previously described operation is repeated with the forward count of the reversible pulse counter 20. In case the monitored voltage exceeds the upper permissible voltage level, then in the direct counting mode, the code at the output of the reversible counter 20 pulses, successively, will increase to equality with the code received from the third inputs 24 of the device. In this case, the equal voltage at the input of the comparator 2 will not. The signal from the output of the comparison circuit 4 will switch the reversible counter of pulses 20 to the Reverse mode, switching the trigger 8, but since the signal of the logical O remains at the comparator output, then the trigger 6 will record the logical O, which will correspond to the signal Not high norm on the second output 26 of the device.

In case the monitored voltage is below the lower permissible level, then in the countdown mode, the code at the output of the reversible counter 20 pulses, decreasing in succession, decreases to equality with the code received from the second inputs

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devices. In this case, the equal voltage at the input of the comparator will not. The signal of the comparison circuit 3 switches the reversible pulse counter 20 to the Reverse mode, switching the trigger 8, but since the output of the comparator 2 remains the logical I signal, the trigger 1 will record the logical 1 signal, which will correspond to the He signal

The norm is based on the VDOBHIO on the first output 25 of the device.

In the next cycle after receiving the signal, the device does not take normal operation, and the measurement result in each cycle will depend on the current level of monitored voltage. 0

Claims (1)

Invention Formula Device for voltage control on aut. St. No. 1183943, which means that, in order to increase the speed of the device, a recording pulse shaper, a switch, a tracer element and a HE element, whose input 0 is connected to the pulse output of the generator of a linearly varying voltage, and the output is connected to the synchronous input of the write pulse former and the input of the delay element, output k,. the second is connected to the gate input of the recording control trigger, the forward output of which is connected to the first control input of the switch, the second control input of which 0 is connected to the inverted output of the recording control trigger, the first information input is connected to the input code of the lower level of the device, the second information input is connected to the output of the upper level code of the device, and the output is connected to the generator variable voltage input, the recording control input of which is connected to the output of a recording pulse of 0 l, the information input of which is connected to the output of the comparator. U