SU1577026A1 - Device for controlling three-phase inverter - Google Patents

Abstract

The invention relates to converter technology and can be used in control systems for three-phase hysteresis electric motors. The purpose of the invention is to enhance functionality and increase reliability. The device contains a master oscillator 1, which supplies pulses to the counting input of the first counter 3 directly, and to the counting input of the second counter 4 via the logical element NOT 2. The output signals from the counters arrive at the inputs of the decoders 5 and 6. The signals from the like outputs of the decoders are summed by the elements OR 7-9 and arrive at the outputs of the device. A major element 10 is connected to the outputs of the device. The output of the latter is connected to the combined inputs of the elements NAND, OR 11, 13, to the other combined inputs of which the inverted frequency F op is fed from the output of the element NOT 2. The outputs of the elements NAND, OR 11, 13 Through the logical element, AND-NOT 12 are connected to the zero inputs of the summing counters of 3.4 pulses. From outputs 14-16, a three-phase inverter is controlled, output 17 is the output of the control circuit. In the event of a malfunction of the device, a sequence of pulses appears at output 17, indicating a failure in the control system. 2 Il.

Description

-, Figure 1

The invention relates to converter technology and can be used in control systems of three-phase hysteresis motors.

The purpose of the invention is to enhance functionality and increase reliability.

FIG. 1 shows a functional diagram of the device; in fig. 2 - time diagrams of the basic elements.

The device contains a generator of 1 pulses, elements NOT 2, binary-decimal counters 3 and 4, decoders 5 and 6, elements OR 7-9, majority element 10, logical elements AND-NOT 11 and 12, element OR 13, positions 14 - 17 - device outputs.

The master oscillator (SG) generates rectangular pulses (fon) with a duty cycle, coming to the counting input of the first counter 3 directly, and to the counting input of the second counter 4 through the element NOT 2. Output signals from the meters arrive at the inputs of the decoders 5 and 6. Signals with the like outputs of the decoders are summed by the elements OR 7-9 and are fed to the outputs of the device. The outputs of the device are connected to the majority element 10, the output of the latter is connected 1c to the combined inputs of the elements AND-NOT 11, OR 13, to the other combined inputs of which the inverted frequency fon is output from the output of the element NOT 2. The outputs of the elements AND-NOT 11, OR 13 through the element AND - NO 12 is connected to the zero inputs of summing counters of 3 and 4 pulses. The outputs of the three-phase inverter control unit are outputs 14-16, output 17 is the output of the control circuitry.

The device works as follows.

When applying the reference frequency from the MH (Fig. 2, fon) to the inputs of counters 3 and 4, binary number codes 0.1 9 are sequentially set at their outputs (Fig. 2a, b). This counting sequence is provided by the feedback from the second bit outputs to the installation inputs. The signals from the outputs of the first and fourth bits of counters 3 and 4 are fed to decoders 5 and 6. At the outputs of the decoders, a three-phase sequence is formed.

0

five

0

five

thirty

35

40

45

50

55

pulses with a shift between the phases of 120 degrees, and the signals at the outputs of the decoder 6 are shifted in time by half the period of the ZG 1 reference frequency relative to the signals at the outputs of the decoder 5 (Fig. 2c, d). When summing the pulses from the same outputs of the decoders by the elements OR 7 - 9 at the outputs of the latter, a three-phase pulse sequence is formed with a shift of 120 degrees / degrees and a duty cycle (Fig. 2e). The majority element 10, connected to the outputs of the elements OR 7-9, forms at the output a sequence of pulses (Fig. 2m), during normal operation of the device, coinciding with the sequence of pulses at the output of SG 1. The AND-NOT elements 11 and 12, OR 13 realize a logical function :

I F (fonvfl) (f0 VM),

where f0 (1 is the reference frequency;

M - signal at the output of the majority element.

In the event of a device malfunction, the information at the output of the majority element is distorted, and a high level impulse is formed at the output of the NAND 12 logic element, setting its countersink 3 and 4 to the zero state with its falling edge, after which the device restores normal operation. In the event of a malfunction of the device, a sequence of pulses appears at output 17, indicating the need for a transition to a backup system or replacement of a converter. Thus, the device actually has a diagnostic system that extends its functionality. The absence of an RS flip-flop (memory element) in the hardware control circuit increases the noise immunity of the device, i.e. reliability of operation.

Claims (1)

Invention Formula A device for controlling a three-phase inverter, comprising a master oscillator, an element NOT, the first element NAND, an output connected to the first input of the second element NAND, characterized in that, in order to expand its functionality and increase its reliability, two summing binary signals are entered into it -des pulse counters, two decoders, four OR elements and the majority element, while the counting input of the first binary-decimal pulse counter is connected to the output of the master oscillator and through the element NOT with the combined counting input of the second binary-decimal pulse counter and the first inputs of the first elements AND-NOT and OR, the second combined inputs of which are connected to the output of the majority element connected by the inputs to the outputs of the second, third and fourth elements OR, connected by the first inputs of the corresponding enno to first, second and third ten 15 the outputs of the first decoder, the second inputs of which are connected respectively to the first, second and third outputs of the second decoder, the first and second inputs of the decoders are connected respectively to the outputs of the first and fourth bits of the corresponding binary-decimal pulse counters, the zero inputs of which are combined with the outputs of the second element And - NO, connected by the second input to the output of the first element OR, and the installation input of each summing binary-decimal pulse counter is connected to the output of its second time p yes