SU1667254A1 - Number-to-time converter - Google Patents

Abstract

The invention relates to automation and computing and can be used in automatic control systems and information conversion and coding devices. The purpose of the invention is to expand the field of application of the converter by ensuring the continuous formation of parallel-serial time intervals. For this purpose, a code-time interval containing a pulse generator, a pulse counter, a register, a control trigger, three D-triggers, a code comparison element and three AND elements, an inverter, an OR element, a fourth, fifth and sixth AND elements as well as a group of elements And (three inputs). 2 Il.

Description

The invention relates to automation and computing and can be used in automatic control systems and information conversion and coding devices.

The purpose of the invention is to expand the field of application of the converter by providing continuous formation of parallel-consecutive time intervals.

Nafig 1 shows the converter code-time signal circuit diagram, FIG. 2 - diagrams explaining his work.

Converter code - time interval contains pulse generator 1, pulse counter 2, register 3, code comparison element 4, control trigger 5, first D-flip-flop 6, first 7, second 8 and third 9 elements And, bus 10 of the input code, first 11 and second 12 output buses, fourth 13, fifth 14 and sixth 15 elements And, second 16 and third 17 D-flip-flops, inverter 18, group of first 19 and second 20 elements And, element OR 21, third output bus 22, output a write resolution bus 23, a write input bus 24. The operation of the code-time converter is explained in the diagram in FIG. 2, where a is the output of the pulse generator 1; b - counter transfer output; c - output of the third D flip-flop 17; g - third output tire 22; d- output p of the element And 14; e-output of the inverter 18; W is the output of the second D-flip-flop 16; h - the output of the first element And 19; and - the output of the second element And 20; to - the output of the second element And 20; k is the output of reference element 4; L - first output tire 11; m - the output of the first D-flip-flop 6; n - the second output bus 12; On exit, bus 23 permits recording.

with

with

Os

about XI th

(L

The timecode converter works as follows

At the output of the counter 2 pulses, all code combinations appear (in the quantity 2P, where n is the number of digits of the counter 2). At the state 11 ..1 in the second half-period of the clock frequency of the generator 1 an active transfer signal is produced (b) Active low level the transfer allows the counting of the second D-flip-flop through an AND 15 element, setting in 1 the third D-flip-flop 17 (c). The second D-flip-flop 16 generates a pulse (g) with a duration in the period of the clock frequency, since it is turned on as a divisor by two. The third D-flip-flop 17 will be switched with a half-cycle of the clock frequency, since the clock pulses will pass through the inverter 18 (e). It will be set to 1 two periods of the clock frequency of the generator 1 because the second D-flip-flop 16 is set to O after a period clock frequency The inverse output of the third D-flip-flop is the third output bus. The signal that will form the element AND 19 of the group (h) as a result of logical multiplication of the second 16, third 17 D-flip-flops and the pulse generator 1 through the element OR 21 will set the first D-trigger 6 in 1 (m) Active 1 of the first D-flip-flop 6 reset to O the control trigger 5 After the second D-flip-flop 16 is set to O, a pulse (s) with a duration of half the period of the clock generator 1 is formed on the second element And 20 of the group The first D-flip-flop 6 will be reset to O. Therefore, during the time when the bus on the 22O bus occurred, the circuit has been replaced by a new code conversion. After the active transfer signal, a counting pulse is generated at the first D flip-flop 6 after a period of the clock frequency of the generator 1. reset to the same D-trigger 6 Log The “1” on the third output bus 22 means that the circuit performs code conversion, while the transition of this bus from O to 1 means that the counter 2 pulses started counting from the 00 O code

When the code of the counter 2 pulses is equal to the register code 3, the code comparison circuit 4 will generate a pulse with a duration in the period of the clock frequency (k), which will set the control trigger 5 to 1, and the first output bus 11 will drop from high to low and the second output bus 12 - conversely, from low to high. Logic 1 at the output of control trigger 5 generates a write enable signal for bus 23 to a device that generates a write signal for bus 24 if the device generates a signal at this time

records, then through the fourth element I 13 will write down bus 10 code to register 3, and the new conversion will produce a new code. The write lock is necessary to prevent the converter from malfunctioning, which may occur if you write a code before register 3 How the Comparison Codes Work

In the general case, at the outputs of the converter, time relationships will be realized.

15

t (1) t (0) N (a) 1/2,

t (2) t (0) N (b) N (a) -1/2

t (3) - t (0) N (b) -1

where N (b) is the size of the counter 2 N (a) is the register code 3 It must be remembered that the time (1) (2), (3) is directly proportional to the register 3 code with a correction of 1/2 clock frequency of the generator 1 for the first 11 and second 12 output buses and for the period for the third output bus 22 This is because the transfer signal shuts off the output buses and the reset signal that is generated

on the second element, And 20, sets the outgoing tire to the appropriate position

The code conversion accuracy — the time interval will be determined by the clock generator 1's permissiveness and the switching error of the second B, the third 9 And elements, and the third D-trigger 17

This converter allows

to form parallel time intervals in parallel automatically, without the support of an external device, which in complex devices where many of these are transformable facilitates the work of the controlling microcomputer

Claims (1)

Invention Formula The converter code is a time interval containing a register, a control trigger, first, second and third D-triggers and a pulse counter, the counting input of which is connected to the output of the first element. And the first input of which is connected to the output of the pulse generator, the information inputs of the register are the input code bus and the outputs are connected to the first inputs of the code comparison element, respectively, the second inputs of which are connected to the corresponding information outputs of the pulse counter, the reset input of which is combined with the reset input sa first D-flip-flop. the counting input of which is combined with the counting input of the control trigger; the reset input of which is connected to the output of the first D-flip-flop, whose information input is connected to the forward output of the control trigger, the inverse output of which is connected to the first input of the second element I, the second input of which is combined with the first input of the third element And, the second input of which is connected to the direct output of the control trigger, the outputs of the second and third elements And are respectively the first and second output buses, characterized in that expanding the field of application of the converter by ensuring the continuous formation of parallel-serial time intervals, the element OR, the fourth, fifth and sixth elements AND, the group of elements AND, and the inverter, whose input is combined with the first input of the fifth element AND, the first the input of the first element I group. and the first input of the first element I, the second input of which is combined with the first inputs of the third and sixth elements I. The third output bus and connected to the inverse output of the third D-flip-flop, the direct output of which is connected to the second inputs of the fifth element And and the first element And of the group and the first input of the second element And of the group, the second input which is connected to the information input of the second D-flip-flop and connected to the inverse output of the second D-flip-flop, the direct output of which is connected to the third input of the first element And group and to the information input of the third D-flip-flop, the counting input of which is connected to the output of the inverter the input is combined with the third input of the second element AND group, the second input of the sixth element And and connected to the transfer output of the pulse counter, the outputs of the fifth and sixth elements And are connected respectively to the counting input and the reset input of the second D-flip-flop, the outputs of the comparison code element and the first AND element of the group are connected by the first and second inputs of the OR element. the output of which is connected to the counting input of the first D-flip-flop, the reset input of which is connected to the output of the second element AND of the group, while the register entry input is connected to the output of the fourth element AND, the first input of which is the write bus, the second input is connected to the forward output of the trigger control and is the output bus resolution recording a 6 d g d JTJ-TjnJ Lnjn rLJJ JT-rLrLrLTL nj jn-jTJOjnj LTTji1 ggp yy FIG. 2