SU1401589A1 - Code to time interval converter - Google Patents

Abstract

The invention relates to a pulse technique and can be used to simultaneously form several signals with a different duty cycle with pulse-width modulation necessary to control a multi-drive device, such as a robot, with a large number of degrees of freedom. The purpose of the invention — extending the functionality of the device — is achieved by increasing the number of simultaneously converting different codes to corresponding time intervals. To do this, a descrambler 8 and triggers 9 by the number of conversion channels with functional connections shown in the drawing are additionally introduced into the device. In addition, the device contains a pulse generator 1, a pulse counter 2, a setpoint generator 3 codes, a storage unit 4, elements 2I-OR 5, a second counter 6 pulses, a unit 7 of code comparison. The introduction of new elements and links allows you to simultaneously convert several different codes into the corresponding time intervals without increasing the number of channels for converting all the elements contained in the device. 2 3. p. F-ly, 4 ill. SS (L

Description

 Hana / ii

Kanap m

ubif.oS

N

ABOUT

sd

OO CD

1 1 the invention relates to a pulse technique and can be used for the single-generation of several signals with a different duty cycle with a pulse-width modulation necessary to control a multi-drive device, such as a robot, with a large number of degrees of freedom.

The aim of the invention is to enhance the functionality of the device by increasing the number of simultaneously converting different codes to the corresponding time intervals.

FIG. 1 shows a functional diagram of the device; in fig. 2 is a pulse counter circuit; in fig. 3-4 time diagrams of converter operation.

The code-time interval converter contains a pulse generator 1, a pulse counter 2, a setpoint generator 3 codes, a storage unit 4, elements 2И-OR 5, a pulse counter 6, a code comparison unit 7, a decoder 8, triggers 9, and the output of the generator 1 pulses connected to the counting inputs of the counters 2 and 6, the lower bits of the counter 2 are connected to the address inputs of the decoder 8, the storage unit 4 and the setting device 3 codes, the information inputs of which are connected to the input buses, and the outputs - with the first inputs of the elements 2I-OR 5, the second inputs of which are connected They are connected with the direct output of the higher bit of counter 2, the corresponding inverse output of which is connected to the third inputs of elements 2И-OR 5, the fourth inputs of which are connected to the outputs of the storage unit 4, and the outputs to information inputs of counter 6, the outputs of which are connected to information inputs of the storage unit 4 and inputs of the code comparison unit 7, the output of which is connected to the recording prohibition input of the storage unit 4 and information inputs of the trigger 9, the counting inputs of which are connected to the corresponding outputs Rattor 8, and exits - with output tires.

The pulse generator can be made on the basis of inverters with resistive-capacitive connections or with quartz stabilization, for example, on a K 155LN1 microcircuit.

The pulse counter 2 is made summing and can be performed on the K 155IE5, K 155LA2 and K 155LN1 microcircuits, for example, according to the scheme shown in FIG. 2

The setting unit 3 codes and the storage unit 4 are made multi-register, with the number of registers corresponding to the number of simultaneously converting different codes, and the register size equal to the input code, for example, on memory chips K 155RU2 whose outputs are connected via load resistors to the power source, but

0

r

0 5

Additional inverters are connected to the information inputs, for example, on К 561ЛН2 microcircuits to compensate for the inverted output signal.

Elements 2I-OR can be performed on K 599 LKZ microcircuits and their number is determined by the width of the input codes.

Counter 6 can be made on the basis of the K 155IE7 microcircuit, block 7 of the code comparison can be made on the basis of the K 155LA2 or K 155LL1 microcircuit, depending on whether the input information is represented by direct or inverse codes.

The decoder 8 can be made on the basis of the K 155IDZ chip, and the triggers 9 - on the basis of the K I55TM2 chip.

When using elements made on other types of microcircuits in the device, the following time relationships should be observed to maintain the device's operability. The signal from the output of block 7 must go to the input of the prohibition to record storage unit 4 before changing the information on its information inputs, and to the information inputs of the triggers later than changing the signals on the outputs of the decoder 8, otherwise the device will not match the output signals to the input.

Converter code - time. The interval works as follows.

The generator 1 and pulses produce pulses arriving at the input of summing counter 2, the minor bits Q, ..., whose QN with a clock frequency of the pulse generator 1 carries out a sequential search of 2 addresses of a multi-register encoder 3, of a multi-register storage unit 4 and decipheror 8. At the outputs Q, ..., QN of the setter 3 of the code and the storage unit 4, the information code of that conversion channel is set at each frequency beat, the address of which at that time is determined by the values of the lower bits Q, ... , Q counter 2. H one of the outputs Q, ..., QM of the decimator 8, corresponding to the conversion channel, whose address is set to its address inputs A -, ..., At at the same time, is a negative polarity pulse, which sets the corresponding trigger 9 in state determined by the signal level at its information input. From the direct P and inverse P outputs of the highest bit of counter 2, connected to the second and third inputs of N elements 2I-OR 5, during the first 2 cycles of the generator 1 pulses, the signal levels are equal to one and zero. Therefore, during the indicated measures, the outputs of the 2I-OR 5 elements, i.e., the inputs D ,, ..., О „of the presetting of the counter 6, receive information codes from the outputs

0

0

five

0

five

Qi, ---, Qn of the dial of the 3 codes and the codes from the outputs Qi, ..., Qw of the storage unit 4 do not pass. Counter 6 changes the value of the incoming to the inputs DI, ..., DH code per unit of the youngest digit in the course of each of the 2 cycles of the generator 1 pulses. Moreover, when the time codes are set by the direct codes on the input bus, counter 6 is made subtractive, and when set by the return codes, it is summing.

From the outputs QI, ..., of the counter 6, the modified code arrives at the information inputs DI, ..., ..DH of the storage unit 4, where it is recorded under the condition that there is no prohibiting zero. The signal level at its input to the Vp recording prohibition. Block 7 of the code comparison with a constant number generates this zero signal level at its output when the signal levels at the outputs Q ,, ..., Q of the counter 6 are equal to a single level in the case of setting time intervals with direct codes and zero if setting with return codes . In addition, the signal from the output of block 7 of code comparison with a constant number arrives at the information inputs of the flip-flops 9, which, if you specify a non-zero duration of the time interval on any channel, allows you to set the flip-flop 9 corresponding to this channel to one state when accessed address of this channel during the first 2 cycles of the conversion cycle.

For the next 2 (2-1) clocks, the signal levels on the forward P and inverse P outputs of counter 2 change their values to opposite. Therefore, these subsequent cycles to the inputs DI, ..., D of pre-recording counter 6 through the elements 2I-OR 5 receive information codes from the outputs Q, ..., QM of the storage unit 4 and the codes from the outputs Q do not pass. , ..., Qrt master 3 codes.

From the outputs Q, ..., Q | j of the counter 6, the re-modified code is fed to the information inputs D, ..., D; j of the storage unit 4, where it is recorded under the condition that there is no inhibitory signal at input V. Thus, the information code any conversion channel stored in the storage unit 4 to the clock cycles at the address of this channel is changed by one least significant bit every time until it becomes equal to the code on the input bus IP, .. ,, NP, corresponding to the time a variable interval of zero duration. From this moment and until the beginning of a new conversion cycle, a zero signal level is established at the output of a block 7 comparing codes with a constant number to the access cycles at the address of this channel, prohibiting the change of the information code in the storage unit 4 and allowing the trigger 9 to be set to zero. corresponding to this channel

Vani. This continues until the 2 () bars have completed. And then the signal levels at the forward P and inverse P outputs of counter 2 again become single and zero, respectively. The outputs of the 2I-OR 5 elements receive information codes from the outputs Q ,,, ..., QN of the setter 3 of the codes, and a new cycle of code conversion to time intervals begins. Thus, the cycle time for converting a code into a time interval is in cycles. The transform discretion is clock cycles. Maximum duration

Ru can be set, make ticks.

time interval which is 2 (2 j-i)

0

five

with

0

0

0

five

Introduction of a code to the converter — the time interval of new elements and links allows for increasing the functionality of the device, i.e., simultaneously converting several different codes to the corresponding time intervals without increasing the number of channels for converting all the elements contained in the device.

Claims (3)

1. Converter code is a time interval containing a pulse generator, the output of which is connected to the input of the first counter, the setpoint generator, the information inputs of which are connected to the input buses, and the outputs are connected to the first inputs of elements 2I-OR, the other inputs of which are connected to the outputs of the storage unit The information inputs of which are connected to the outputs of the second counter, a code comparison unit whose output is connected to one of the trigger inputs, characterized in that, in order to expand the functionality of the devices by increasing the number of simultaneously converting different codes into the corresponding time intervals, additionally entered a decimator and triggers according to the number of conversion channels, and the direct output of the high bit of the first counter is connected to the second inputs of the 2I-OR elements, and the inverse to the third , the fourth inputs of which are connected to the outputs of the storage unit, and the outputs to the information inputs of the second counter, the counting input of which is connected to the output of the pulse generator, and the outputs to the inputs of the block are compared and codes whose output is connected to the prohibition input of the storage block and information inputs of the triggers, whose outputs are connected to the output buses, and the counting inputs to the decoder outputs, the inputs of which are connected to the address inputs of the code setters and the storage block and the low-order outputs of the first counter . 2. The converter according to claim 1, characterized in that the second counter is made subtractive, the code comparison unit is made as an AND-NOT element, and the time intervals are set by direct codes. 3. The converter according to claim 1, characterized in that the second counter is made summing, the code comparison unit is made as an OR element, and the time intervals are specified by inverse codes. Srig.G.