SU1649659A1 - Frequency divider with programmed count-down ratio - Google Patents

Abstract

The invention relates to a pulse technique and can be used in devices for automatic control and synthesis of frequencies. The purpose of the invention is to increase speed and reliability and performance. The frequency divider contains the control unit 1, the recognition unit 2, the 3 higher bits counter, the first and second code recording blocks 4 and 5, the output bus 6, the 7 low bits counter, the input bus 8, the code buses 9, 10 and 11 high bits Dov, Converter 12 binary code in the Gre code, code bus 13 and 14 low bits. 2 Il.

Description

The invention relates to a pulse technique and can be used in devices for automatic control and synthesis of frequencies.

The purpose of the invention is to increase the speed and reliability of operation.

FIG. 1 shows a frequency divider block diagram; in fig. 2 - time diagrams that show the work of the divider.

The frequency divider contains the control unit 1, the recognition unit 2, the 3 higher bits counter, the first and second code recording blocks 4 and 5, the output bus 6, the 7 low bits counter, the input bus 8, the code buses 9, 10 and 11 high bits Dov, Converter 12 binary code in the Gre code, code bus 13 and 14 low bits.

The first input of the control unit 1 is connected to the output of the identification unit 2, the second and third inputs are connected to the bit outputs of the 7 lower order counter, the fourth input is connected to the input bus 8 and the exit of the counter of the lower 7 bits, and

the output is with the output bus 6 and the recording resolution inputs of the first and second blocks 4 and 5 of the code record. The inputs of the identification block 2 are connected to the bit outputs of the 3 high bits counter, the synchronization input of which is connected to the 7 low bits counter output, and the information inputs to the outputs of the first block 4 of the code record, whose information inputs are connected to the code buses 9, 10 and 11 senior bits.

The information inputs of the counter 7 low-order bits are connected to the outputs of the second block 5 of the code record, the information inputs of which are connected to the outputs of the binary code converter 12 to the Gre code, the inputs of which are connected to code buses 13 and 14 of the lower bits.

In this case, the counter 7 is a two-bit counter in the Gre code, the counter 3 is a three-bit binary counter, or (n - 2) is the bit where n is the number of bits

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divider Counters 3 and 7 operate in subtraction mode.

The frequency divider works as follows.

FIG. 2 shows the time diagrams of the input sequence CKL (Twx), the output signals a and b of the counter bits 7 lower bits, the output signal from the identification block 2 (circuit I (n - 2) -inputs), the output signal d of block 1 control, and for a division factor of seven, it suffices to consider three four-cycle cycles Tc1, TC2, Tcz of operation of the divider. With Kdel 7, the number three is entered into the counter 7, and the number one is entered into the counter 3.

The period of division of Tr consists of seven cycles. In the first cycle of each division period, the two cycles Ti, T2 refer to the previous division period, and in the last cycle of the division period the last two cycles Tc, T4 refer to the next division period. The two cycles of Tz and J4 of the first TC1 cycle are intended to set a new division factor. The number of cycles of the second TC2 cycle is equal to the remainder of dividing the division factor of the divider by four. With a balance equal to zero, the second TC2 begins with the first clock cycle TI, with a remainder division equal to three, the cycle TC2 begins with the second clock J2, with a remainder division equal to two - from the third clock Tz, with a remainder division equal to one — from the fourth tact Tz. This mode is provided by the reverse operation of the counter in the Gre code. The duration of each next cycle, except the last one, is equal to four cycles.

Counter 7 operates in the Gra code in subtraction mode. The clock ti corresponds to the state of the counter three, the clock T2 to the state two, the clock Tz to the state one, the clock T4 to the state zero. In the second cycle T2 of the last cycle of the division period Tp, the pulses of all three sequences a, b, c take the values of log 1. In this cycle, control unit 1 is activated and, starting from the next cycle Tz, the output of the unit 1 pulse of one and a half cycle duration ( sequence d). The sequence d controls the recording of a new division factor in counters 3, 7. During this time, a new division factor is established in the counters. In our case, the counter 7 sets the code three, 7mod4 3 (in the diagram, the coefficient setting process is shown by dashed lines). Since the next state of counter 7 is two (11 in the Gre code), the second TC2 cycle begins with the T2 clock (in

the sequences a and b contain log 1) and therefore an empty graph appears on the diagram. Counter 7 operates in a cycle of 10 11 01 00 10 11 ... If the division ratio would be six, then the TC2 cycle began with a clock cycle Tc and the first two columns would not be filled with the graphical diagramming form adopted.

Triggers counters 3 and 7. They have an advantage on the inputs of installation 0 and 1 relative to the synchronization input. Record the division ratio, i.e. The initial states of the triggers of counters 3 and 7 are uniquely assigned to the inputs of set 0 and 1. The division factor is entered into counters 3 and 7 in the forward binary code. The smallest division factor is 3, and the largest (2 - 1).

The speed of the divider is ensured by the fact that the pulses of logical states are generated with a delay equal to one transition of a logical element from one state to another. The pulses acting on the control unit 1 are generated in one half-cycle, and in the second half-cycle a control impulse is produced, which already performs a logical operation in the first half-cycle of the next clock cycle. A counter operating in the Gre code, for one clock cycle, changes the state of only one trigger. Therefore, the pulse delay in the two bits of the counter in the Gre code for all four states is the same. Another important factor is the reliability of operation of the divider, which is ensured by the selectivity of the operation of the low-order counter units of the divider and control unit during the period of the division. This is achieved by texturing and splitting the input sequence into loops.

Claims (1)

Invention Formula A programmable dividers frequency divider containing a control unit, the first input of which is connected to the output of the identification unit, whose inputs are connected to the bit outputs of the high-order counter, the information inputs of which are connected to the outputs of the first code writing unit, the control input of which is connected to the output of the control unit, the recording resolution input of the second code writing unit and the output bus, the low-order counter, whose information inputs are connected to the outputs of the second recording unit, the output is input of counter synchronization MSB, and outputs The discharge - the second and third inputs of the control unit, whose fourth input is connected to an input bus, wherein the data inputs The first code writing unit is connected to high-order code buses, characterized in that, in order to improve speed and reliability, a binary code converter is inserted into the Gre code, whose inputs are connected to low-order code buses, and the outputs are to information inputs the second code writing unit, while the low-order counter is made with a two-bit counter in the Gre code, the synchronization input of which is connected to the input bus. 1 Tc, .L 6Tsg Tc, G G b T ъ т2 73 ;;