SU1272501A1 - Pulse repetition frequency divider - Google Patents

Abstract

The invention can be used in devices of automation and measuring equipment. The purpose of the invention is to increase the uniformity of the output frequency. The frequency divider contains the element 1 BAN, the counter 2 of the integer part of the division factor, the adder 4, the source 5 of the code of the fractional part of the division factor. Introduction to the device of the counter 3 pulses with a corresponding connection to the adder when specifying the fractional part code of the division ratio in the form of binary fractions makes it possible to significantly simplify the circuitry of the device. The execution of the adder 4 and the counter 3 pulses are reversible and the introduction of an additional element SAS S PRET expands the functionality of the device by providing (L or reverse operation mode. 1 3.pf files, 2 ill.

Description

one

The invention relates to a pulse technique and can be used in automation and measuring devices,

The purpose of the invention is to increase the uniformity of the output frequency while simplifying the device and extending the functionality by providing reverse mode operation.

Figure 1 shows an electrical structural diagram of a pulse frequency divider; figure 2 is the same for the case of reverse operation mode.

The device contains the element I BANGE, the output of which is connected to the clock input of the counter 2 of the integer part P of the K division factor, the output of which is connected to the input of the counter of 3 pulses; the bit outputs of the counter of 3 pulses are connected in reverse order (the first with the last, the second with the penultimate {them, etc., until the last with the first) with the bits of the first group of inputs of the adder 4, the bits of the second group of inputs of which are connected with the corresponding outputs of the source 5 code fractional part of the division factor; the first input element 1 BANGE is connected to the input bus 6, the second input is connected to the output (transfer) of the adder 4; the output bus 7 is connected to the output of the counter 2 of the integer part of the division factor.

The counter 2 of the integer part of the division factor to provide a change in the value of this integer part can be made as a frequency divider with a variable division factor, the information inputs of which are connected to the code bus of the integer part of the division factor.

For the organization of the reverse mode of the pulse frequency divider, an additional element 8 BANCH is introduced into it, input and output buses 9 and 10, and counters 2 and 3 of the integer part of the division factor and pulses, respectively, are reversible; the first input of the additional element 8 BANGE is connected to the additional bus 9, the second input to the output of the adder 4, the output to the additional clock input of the counter 2 of the integer part of the division factor, the additional

725011

the output of which is connected to the auxiliary input of the counter of 3 pulses and to the additional output bus 10. The device operates as follows

5 way.

Pulses from the bus 6 of the frequency to be divided (with the exception of those blocked by element 1) are sent to the clock input of the counter

10 2.

Pulses of a divided frequency from the output of this counter pass to bus 7 and to the input of counter 3. Counter 3 successively passes all possible states, the number of which for a n-bit (binary) counter is 2 M. Consequently, during the formation time M output pulses of the device on inputs 20 A, ..., A of adder 4 in some order form all n-bit binary numbers. The inputs B,, ..., Bj of the adder 4 are continuously supplied with the number N equal to the binary

25 recording the fractional part of the division ratio.

Consequently, during the formation of the M output pulses of the device, the overflow signal of sum 30 of torus 4 is generated N times. This signal is applied to the Inhibit of element 1 input and causes a blocking of one input pulse.

At the same time, the channel of the device, formed by element 1 and counter 2, divides the input frequency either by P (if there is no prohibition) or P + 1 (if the output / signal of counter 2 described in the described way led to the formation of the prohibition).

During the time M of the output pulses of the device, the prohibition was formed N times and was absent (MTY) times and, consequently, the number of input pulses of the device during this period amounted to

N (P4-1) + (M-N) P PM + N

The average dividing ratio of the device is

J u K P 4 -Nf. M M

or, considering that M 2, and the transition from a simple fraction to a binary fraction,

K P, N.

Connecting the counter outputs to the 3 inputs of the adder 4 in the reverse order does not change the average coefficient

Claims (2)

The claims 20 I. Pulse repetition rate divider containing the FORBID element, the first input of which is connected to the input bus, the second - with the output of the sum-25 torus, the output - with the clock input of the counter of the integer part of the division coefficient, the output of which is connected to the output bus, and the fractional code source part of the division coefficient, which is characterized by the fact that, in order to increase the uniformity of the output frequency while simplifying the device, a pulse counter is introduced into it, the input of which is connected to the output bus, the bit outputs from the 1st to the 5th with the first gro the solder of the inputs of the adder, from η to the 1st digits, respectively, the second group of inputs of the digits of which are connected to the corresponding outputs of the code source of the fractional part of the division coefficient. 2. Divider pop. 1, distinguished by the fact that, in order to expand the functionality by providing a reverse mode of operation, the counter of the integer part of the division coefficient and the pulse counter are made reversible and additional input and output buses and an additional element BAN are introduced, the first input of which connected to an additional input bus, the second input to the output of the adder, the output to an additional clock input of the counter of the integer part of the division coefficient, the additional output of which is connected to an additional input of the counter pulses and with an additional output bus. <Put2