SU1525861A1 - Digital synthesizer of varying frequency - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is the formation of piecewise continuous functions for varying the frequency of the output signal while at the same time increasing the accuracy of the approximation. The synthesizer contains memory blocks (PSU) 1,4,7 and 17, sensor 2 of the signal duration code, divider 3 frequencies with a variable division factor, sensor 5 of the frequency range code, dividers 6 and 10 frequencies with a fractionally variable division factor, sensor 8 code of the initial frequency, reversible counter 9, phase increment counter 11, calculator 12 amplitudes, D / A converter 13, frequency divider 14, counter 15, sensor 16 for address of the function and specifying grs 18. The specified function of the output frequency is divided into L linear sections, taking into account the counter size P of 15. Each linear segment is independent Simultaneously from the adjacent has its duration T _I , the frequency range D _I and the initial frequency F _HI . These parameters through BP 1,4, 7 and 7 and sensors 2.5 and 8 are entered respectively into dividers 3 and 6 and counter 9. For a piecewise-continuous function, only initial the value of F _H and the initial values of F _HI at the break points T _J. The goal is achieved by the introduction of BP 4 and 7. 2 Il.

Description

"M /

The invention relates to radio engineering and can be used to obtain an arbitrarily varying frequency, including the formation of a piecewise continuous function of frequency change in various communication systems, sonar, computing and measuring devices,

The purpose of the invention is to form a piecewise continuous function of varying the frequency of the output signal while at the same time increasing the accuracy of the approximation.

FIG. Figure 1 shows the structural electrical circuit of the proposed digital synthesizer of varying frequency; in FIG. 2, an arbitrary piecewise continuous function of

neither the output frequency with the optimal approximation (uneven in time and frequency) with L 16, where L is the number of linear sections, and three discontinuities of the first kind at points t, t,

t ".

The digital frequency synthesizer contains the first block 1 of memory, a sensor 2 of the signal duration code, a divider 3 frequencies with a variable division factor (DDC), a third block 4 of memory, a sensor 5 of the frequency range code, the first divider 6 frequencies with a fractionally variable division factor ( DDPK), fourth block of memory 7, sensor 8 of the code of the initial frequency, reversible counter 9, second divider

10 frequencies with fractional variable division ratio (DDPK), counter

11 phase increments, 12 amplitude calculator, digital-to-analog converter (D / A converter) 13, frequency divider

14, counter 15, sensor 6 function address 6, second memory block 17, dach generator 18,

The variable frequency digital synthesizer operates as follows.

The given function of changing the output frequency (FIG. 2) is divided into L linear sections taking into account the pitch of the counter 15. Each linear section, regardless of the adjacent one, can have its own duration tj, frequency range Dj and initial frequency. These parameters through memory blocks 1, 4, 7 and sensors 2, 5, 8 codes are entered, respectively, through the installation inputs in DCPD 3, DDPD 6 and reversible counter 9.

For a piecewise continuous function, f (t) in the areas of its continuity at the boundaries of adjacent sections of the frequency coincide, at points t of discontinuity of the first kind f (tj - 0) f (tj + 0). In fact, we are not dealing with an ideal piecewise continuous function. , and the function having in the area of points tj (in FIG. 2, points t, t, t) abrupt jumps of the function in the interval tt between the pulses at the output of the DDPC 10.

Il2i 2

.tj

T with

about

five

ABOUT

Q

with

,

five

where Tc t / fc;

 - division ratio

 the second DCPD 10; QJ - code on the installation input of the reversible counter 9, corresponding to; 2 - capacity DDPK 10. Thus, in the reversible counter 9 through the memory block 7 and the sensor 8 it is enough to enter only the initial value f and the initial

Frequency cuts at break points (

t:, putting all of them into the reversible counter 9 is redundant, which, however, increases the reliability of the operation due to the self-restoration of the function with random co0s in the path of its formation.

The pulses from the PDKD 3 output go simultaneously to the input of the DPDK 6 and to the input of the frequency divider 14. After 2 pulses, for each i-th linear section of the function at the output of the PDKD 3, the duration of the section, 2 k, cТ5, where T, l / fg, at the output of DDPK 6, the frequency range D: 8 is processed, counter 15 increments by one and through blocks 1,4,7 of memory and sensors 2,5,8 codes selects new coefficients Kj () simultaneously at the output of the shift memory block 17 is (confirmed) the sign of the increment of the pulses arriving at the counting input of the reversing counter 9,

The code change on the p-discharge outputs of the counter 15 provides in the device an approximation of the function by linear segments with independent G 2: K.,; and 4, t ui Thus, provide-. optimal for error and size 1, p blocks of approximation515

qi function to change the output frequency.

The duration of the processed signal, c, is defined as the sum, the number of pulses N at the output of the first DDPC 6 and entered at the input of the reversible counter 9 - as the sum,

where 1 1,2, .., 2. It is convenient to choose K codes that are numerically equal to D, then N numerically corresponds to the sum of the increment modules by the deviation D for the time TC.

In the reverse counter 9, code Q

Capacity 2 DCPD 10 is determined based on the required increment increment of frequency equal to the minimum possible output frequency

l M

mi //

  while the value of

W, as a rule, is taken equal to 6-8 to ensure the required spectral purity of the signal at the output of the D / A converter 13, When overflow, the counter is 15, and

respectively, and the remaining blocks are set to their original state, thereby ensuring that a periodic repetition

during time i, it varies from its continuous bezel of the output frequency.

By changing the code at the output of the sensor 16 of the function address, it is possible to provide a sequential enumeration of all functions, 20 stored in a digital synthesizer of varying frequency through a sequence of parameters t,, D ,, and the increment signs of linear sections.

initial to the final value with the rate of arrival of pulses at its counting input, the signs of the increment at the input of controlling the reversal of its jumps in the discontinuity points t. 1 function of changing the result code at the output of the reversible counter 9 corresponds to the linear-stepwise approximation of the piecewise continuous function of changing the output frequency- 25 Blocks 1, 4, 7, 17 of memory can

You are in the areas of its continuity. I

Testing areas T with zero

the increment of the deviation (the portion of the tonal signal) is provided by applying to the installation inputs of the DCPD 6 K 0.

The synchronization frequency pulses f are received from the second output of the master oscillator 18 to the clock input of the second DDPK 10 with a capacity of 2, the average frequency of the pulses at the output of which is f, ftQ / 2. Phase increment counter 11 with a capacity of z counts the number

pulses arriving at its input, the complete filling of the counter 11 corresponds to the count of the period of the sinusoid of the output frequency igux of the synthesizer.

The calculator 12 amplitudes convert the continuously increasing numbers of the counter 11 phase increments into the current digital amplitude values, which are converted by the CL 13 into a continuous output signal with a frequency fg fcQ / 2,

The bits 1 and p are chosen from the conditions for ensuring the necessary accuracy of the approximation of the original function. The larger the p, the more linear approximation plots. Than

the greater the 1, the greater the deviation can be set55 The output frequency of these dividers can be set in the i-th linear section, but is defined as the product of the input-simultaneously decreases the minimum frequency by the ratio of the number (value when set-up) recorded on the control panel f- - 1 / Te.voddy, to the capacity of the divider.

be made on the basis of semiconductor permanent or operative memory devices with random sampling, into which are inserted

respectively, the required addresses of access to the sensors 2, 5, 8 or directly the output parameters of the sensors 2, 5, 8, as well as a one-bit control code for the reversing counter reversal 9. In this case, similar blocks can be used as sensors 2, 5, 8 memory in which are listed. parameters of signal duration, frequency range and initial frequency.

or parallel registers (repeaters) of signals. The sensor 15 is of the same type as the other sensors and is used to provide a quick change of functions from among those recorded in the device through their parameters.

DPKD 3 can be performed on the basis of any recalculation scheme. 50 DDPK 6 and 10 are made either on the basis of a cumulative adder using an overflow output or divisors like binary multipliers, code-often converters10

15

20

25

The reversible counter 9 is made according to a conventional counting circuit having control inputs of presetting the code and the direction of its increment at the initial moment, as well as the reverse when changing the sign of the increment to another,

Counters 11 and 15 are common binary counters. The capacity of the phase increment counter 1 is equal to the number of samples of the sinusoids, the function per period. The number p of counter bits 15 is determined by the number of linear portions L 2 of the function being approximated. If necessary, the counter 15 can be arranged for 2 L; 2 bits

The bit of frequency divider 14 coincides with the bit of DDPC 6, Therefore, frequency divider 14 is a common binary divider.

The calculator 12 amplitudes can be performed either on the basis of a random-selection block with random sampling, in which samples of the current amplitude of a sinusoidal function are recorded within a period, or implemented on the basis of a special calculator of sinusoids in quadrants, using, for example, a linear-step approximation of output 11 signal

ZDL 13 is implemented, for example, on the basis of an integrated circuit chip ZDL 10

Generating generator 18 is, for example, a quartz oscillator with two frequency dividers providing output frequencies fg and fc,

The proposed digital varying frequency synthesizer makes it possible to synthesize the varying frequency of both continuous and piecewise-e-discontinuous functions while simultaneously improving the accuracy of approximation of the required function of measuring the output frequency.

Equivalent Formula

Digital synthesizer of varying frequency, contents sequentially (United signal signal length code sensor, frequency divider with variable division factor, del30

35

40

45

0

five

0

five

0

five

0

five

frequency coupler and counter, serially connected frequency code sensor, first frequency divider with fractional variable division factor, reversible counter, second frequency divider with fractional variable division factor, phase increment counter, amplitude calculator and digital-analogue converter, as well as initial code sensor frequencies, the bit outputs of which are connected to the corresponding setup inputs of the reversible counter, the function address sensor, the first and second memory blocks, the first groups of inputs which are connected to the bit outputs of the function address sensor, and the output of the second memory block is connected to the control input of the reversing counter reversal, the master oscillator, the first and second outputs of which are connected respectively to the clock inputs of the variable frequency divider and the second frequency divider from fractional variable division ratio, with the second groups of inputs of the first and second memory blocks being connected to the bit outputs of the counter, tl and h and y with the fact that, in order to form a piece but the continuous function of changing the frequency of the output signal while simultaneously improving the accuracy of the approximation, the third and fourth memory blocks are introduced, the first groups of inputs of which are connected to the bit outputs of the function address sensor sensor, and the second groups of inputs to the bit outputs of the counter, while the outputs of the first, third, and fourth memory blocks are connected to one-by-one address inputs, respectively, of the signal length code sensor, frequency range code sensor and initial frequency code sensor, output a frequency divider with a variable division factor is connected to the clock input of the first frequency divider with a fractionally variable division factor, and the output of the frequency divider is connected to the preset input of a reversible counter.

   III I1, I - 1 JI J-I - /

t 9%

Fi & 2

Claims (1)

Claim A digital synthesizer of varying frequency, which contains a series-connected sensor for the signal duration code, a frequency divider with retrained division coefficient, a frequency divider and a counter, series-connected sensor of a frequency range code, a first frequency divider with a fractionally variable division coefficient, a reversible counter, and a second frequency divider with a fractionally variable division coefficient, a phase increment counter, an amplitude calculator and a digital-to-analog converter, as well as an initial frequency code sensor, pores whose output outputs are connected to the corresponding installation inputs of the reversible counter, the function address sensor, the first and second memory blocks, the first groups of inputs of which are connected to the bit outputs of the function address sensor, and the output of the second memory unit is connected to the control input of the reverse counter, the master oscillator, the first and the second outputs of which are connected respectively to the clock inputs of a frequency divider with a variable division coefficient and a second frequency divider with a fractionally variable coefficient division, and the second groups of inputs of the first and second memory blocks are connected to the bit-wise outputs of the counter; therefore, in order to form a piecewise continuous function of changing the frequency of the output signal while increasing the approximation accuracy, the third and the fourth memory blocks, the first input groups of which are connected to the bit outputs of the function address sensor, and the second groups of inputs to the bit outputs of the counter, while the bit outputs of the first, third and fourth memory blocks These are connected to the bitwise address inputs of the signal duration code sensor, frequency range code sensor, and initial frequency code sensor, the output of the frequency divider with a variable division coefficient is connected to the clock input of the first frequency divider with a fractionally variable division coefficient, and the output of the frequency divider is connected to the input pre-installation of a reversible counter.