SU1674376A1 - Code to pulse-width signal converter - Google Patents

Abstract

The invention relates to automation and computing and can be used in digital automatic control systems. The purpose of the invention is to expand the conversion range. The converter contains a pulse generator, two pulse counters, two D-flip-flops, an AND element, an OR-NOT element, an input and an output bus. A code converter into a pulse width signal allows converting input codes in the interval from 00 ... 0 to 11 ... 1. 2 Il.

Description

The invention relates to automation and computing and can be used in digital automatic control systems.

The aim of the invention is to expand the conversion range.

FIG. 1 shows a block diagram of a code to pulse-width signal converter; in fig. 2 - diagrams explaining his work.

The code converter into a pulse-width signal contains a generator of 1 pulses, counters 2 and 3 pulses. D-triggers 4 and 5, the element And 6, the element OR - NOT 7, input bus 8 and output bus 9.

The operation of the code-to-pulse-width converter is explained in the diagram in FIG. 2 for the case when the first 2 and second 3 counters are equal to 4. In FIG. 2 marked: and the output of the generator 1 pulses; b is the output of the youngest bit of the first counter 2; in the transfer output of the counter 2, g inverse output of the 0-flip-flop 4: d - the output element And 6; e exit of the loan counter 3, and - the output of the element OR NOT 7; to the output of the D-flip-flop 5 (output bus 9)

The converter works as follows.

Counter 2 passes through all its 2P states, where n is the number of bits of the counter. In the second half of the time interval, when counter 2 is set to state 11..1, a transfer signal is generated, which writes the code from input bus 8 to counter 3 and sets D-flip-flops 4 and 5 to 1. This determines the starting time of each period of the pulse-width signal. D-flip-flop 4 and the AND 6 element prohibit the passage of a single pulse to the subtracting input of counter 5. In the second half of the time interval, when counter 3 is set to the state 00 ..0, a loan signal is generated, which through the element OR-NOT 7 sets to O D-trigger 5 and thereby completes the formation of a pulse-width signal.

The duration of the positive pulse generated on the output bus 9

fc

Os

2

GO VI O

the second D-trigger 5 is determined by the formula.

T (N + 1) t.

where N is the code on the input bus 8,

t is the period of the pulse generator 1

When the code on the input bus 8 is equal to 11 .. 1, the pulse duration at the output of the second D-flip-flop 5 is 1, since the transfer pulses of the counter 2 and the borrowing of the counter 3 are formed simultaneously. But because the loan signal comes through the element OR NOT 7 the clock input and the carry signal are set, then D-flip-flop 5 is not reset in O. The element OR NOT 7 serves to form a pulse to the clocked input of the D-flip-flop 5 with the code 00. .0 on the input bus 8.

The number of bits of counter 3 must not exceed the number of bits of counter 2.

The converter allows any code on the input bus 8 in the range from 00 0 to 11.1 to be converted into pulse width.

Claims (1)

The invention of the code Converter in the pulse-width signal containing the first pulse counter, pulse generator, output which is connected to the first input of the element And, and the second pulse counter, the setting inputs of which are the input bus, characterized in that, in order to extend the conversion range, He entered the first and second D-flip-flops and the element OR-NOT, the first input of which is connected to the output of the second pulse counter, the second input is combined with the summing input of the first pulse counter and connected to the output of the pulse generator, and the output is connected to the C-input of the second D -trigger whose D-input is combined with the D-input of the first D-flip-flop and is a zero potential bus, direct the output is an output bus, and the S-input is combined with the S-input of the first D-flip-flop and the recording input of the second pulse counter and connected to the transfer output of the first pulse-counter whose lower-bit output is connected to the C-input of the first D-flip-flop whose inverse connected to the second input of the element And the output of which is connected to the subtractive input of the second pulse counter FOR IffO PI 0000 0001Q01QN-f N N4PY //// 0000 JT lJTJ- | JrLnj: ... JlJ-Lf-LTLTLrГгКККг b in N-f H-l lt-3 iplIhJ-diJ 000 f 0000 If ft fffO .JruKKhj-u. T (n + t) t fig.Ј