SU1314457A1 - Integrating analog-to-digital converter - Google Patents

Abstract

The invention relates to a measurement technique, in particular to analogue converters, designed to convert voltage into a digital code in digital information processing systems, transient recorders, and the like. The purpose of the invention is to reduce the conversion time. For this purpose, an integrating analog-to-digital converter containing a source 1 of the reference voltage, the first 3 and second 4 keys, a comparator 9, a generator of 6 counting pulses, an integrator 8, a control unit 10, a result counter 13, the elements 2И-OR 7, OR are entered 11 and 12, the comparator 5 and the source 2 of the reference voltage. This made it possible to combine the process of integrating the converted signal and the compensating reference polarity in the first integration interval. 2 Il. S (L 00 4 4 ;; sd Figure 1

Description

eleven

The invention relates to a measurement technique, in particular, to analog-to-digital converters (ADC) for converting voltage into a digital code in digital information processing systems, transient recorders, etc.

The purpose of the invention is to reduce the conversion time.

FIG. 1 is a diagram of the proposed device; FIG. 2 - timing diagrams explaining the operation of the scheme.

The device contains sources 1 and 2, the reference voltage, keys 3 and 4, comparator 5, generator 6 of counting pulses, element 2И-OR 7, integrator 8, comparator 9, control unit 10, elements OR 11 and 12, counter 13,

The device works as follows.

In the initial state, the keys 3 and 4 are open, the counters of the result in all bits are filled with zeros. The duration of the first cycle integration T1. During the first clock cycle, key 3 closes and simultaneously with the help of comparator 5, the voltage U under study is compared with the output voltage of source 2. The output voltage of source 2 is equal to half the ADC scale. The comparator generates a signal if the input voltage exceeds U , (fig. 2 a, b). The presence of a signal at the first output of the comparator allows the passage through the element 2I-OR 7 of the counting pulses from the generator 6. Then these counting pulses through the element OR 11 are fed to the input of the counter 13, Simultaneously According to the signal generated at the second output of the comparator 5 and passing through the IL 12 element, the key 4 closes. Thus, at the interval t ,, - t, the integrator charge through the key 3 and the discharge through the key 4 occur simultaneously, At time t, j the comparator 5 returns to the initial state, the key 4 is opened, the arrival of the counting pulses to the counter input is stopped, the remaining first cycle time the key 3 remains closed, the integrator is charged only by the voltage Ux, By the end of the first cycle

I u + A-sin (Cot + tf) dt +

144572

the voltage on the output of the integrator takes the value

„

8b RC

5 Y °

+ .sin (Gzt + q) -COL dt +

 t-ft

+ and + A-sinCut + tp) dtV

r i, j

  u, + A-sin (cot + 4) l dt 10

RC

1-RC RC °

(4-t,),

i5 where A-sin (wt + t |) is the interference signal,

During the interval, the input of the counter 13 receives N pulses:

20

N, f ,. (,)

where f is the pulse frequency of the counting pulse generator. The second is: integration begins at time t, when

5 to the command from the control unit, the key 3 is opened, and the key 4 is closed. The second integration cycle ends at time t, when all the keys are deactivated by a command from the control unit. Duration of the second integration cycle

Bs

yr x

 about

j Ux + A-sin (ut + t) ldt-Uon (,)

and

on

40

The result N, entered into the result counter, consists of two summed parts: N, (the result of the first integration cycle) and N (the result of the second integration cycle):

45

i

N, f, (

, + A. sin (cot + q) -U (4-ti

N f ---

2. I

U.

0 in the case of equality of the capacities of the counter 13 result and the counter of the control unit

N N, + N2 f, (,) +

ii

+ f

j U; 4-A.sin (ut + 4) dt

-on

: -f, (t, -t,)

and

 t) A-sin (cot + 4) dt

and"

f,

If the period of the interference signal f sin ((0t + if) is t j - t, then

3

j A-sin (ot + t |), i.e. suppression

io

the noise in the proposed device remains the same as in traditional push-pull ADCs.

The total conversion time is reduced due to the fact that part of the result N is already determined during the first integration cycle. Thanks to this, the maximum duration of the second cycle is halved.

To eliminate the error due to the non-synchronization of the interval t, j, ti | Gating of the comparator 5 on the third input by the output pulses of the generator 6 is applied. For normal operation, the capacity of the counter 13 is chosen to be equal to the capacity of the counter of the gravity unit, and the pulses at the outputs of the generator 6 of the counting pulses are shifted by half their follow-up period.

Claims (1)

Invention Formula An integrated analog-to-digital converter containing a first key whose information input is an input bus and the output is 144574 is connected to the first input of the integrator, the second input of which is connected via a second switch to the output of the reference voltage source, and the output through 2 of the comparator is connected to the first input of the control unit, the second input of which is connected to the first output of the counting pulse generator, and the first output is connected to the control the entrance 10 of the first key, characterized in that, in order to reduce the conversion time, elements 2И-OR, OR, a result counter, an additional source of voltage support and a comparator are entered into it, the first input of which is connected to the output of an additional source of reference voltage, the second input is with input bus; the third input is combined with 20 by the first input of the 2I-RShI element and connected to the second output of the counting pulse generator; the first output is connected to the second input of the 2I-OR element; the second output is connected to the first input of the first OR element, the second input of which is connected to the second output of the control unit, and the output to the control input of the second key, the third output of the control unit is connected 30 to the first input of the second OR element, the second input of which is connected to the output of element 2И-OR, and the output is connected to the input of the result counter, and the third input of element 2И-OR is connected to the control with the input of the first key. U kinship but You) (optm spyor 5 W zah yes umesfaimra 6 Bsd integrated Result Counter Input (()