SU1229966A1 - Reversible converter of binary code to binary-coded decimal code - Google Patents

Abstract

The invention relates to digital computing and can be used in information converting devices. The aim of the invention is to simplify and expand the range of stable operation of the converter. The goal is achieved by the fact that in the converter, mounted on reversible counters, the indicator of the end of the conversion is the loan signals and the fact that an input switch for switching the clock signals is entered into it, a block; bindings of control signals to the clock frequency and error correction trigger. 1 il.

Description

The invention relates to digital computing and can be used in devices designed to convert information.

The aim of the invention is to simplify the converter and spread its stable operation area.

The drawing shows the block diagram of the proposed Converter.

The converter contains elements ZI-NOT 1 and 2, elements 2I-NOT 3 and 4, elements NOT 5-7, reversible binary-decimal counter 8, reversible binary counter 9, shaper 10 pulses, element 11, triggers 12-14, element 15, input 16 of the operating mode of the converter, input 17 of the start of the converter, clock input 18 of the converter, inputs of the binary-decimal code 19, outputs

20 binary decimal inputs

21 binary code, outputs 22 binary code, input 23 of the logic zero of the converter.

The Converter operates as follows.

If a conversion of a binary-decimal code to an i-binary is required, then the information inputs of the binary-decimal counter 8 are fed to the inputs 19 of the binary-decimal code, and a zero logic level is set at input 16.

The conversion process begins with the arrival of the signal received at input 17. At this, on its front (transition from a zero logical level to a single level), counters 8 and 9 are set to the initial (zero state), and also trigger 12, to the R input of which this moment comes zero logical level with the output of ele10

15

20

the passage of subsequent clock pulses through the element And 15.

Thus, due to the trigger 13, the start of the conversion process is synchronized with the moment of the clock pulses, which ensures that only the pulses of the same duration pass through the AND 15 element. In addition, the switching of the trigger 13 leads to a change in the information on the D input of the trigger 14. As long as the trigger 14 is in the zero state, the passage of the clock pulses through the NE-NE elements 1 and 2 to the direct count inputs of the reversible counters 8 and 9 is blocked. At the same time, the zero logic level from input 16 prohibits clocking pulses through element 2И-НЕ 4 to the input of the reverse counting of the reversible binary counter 9 and duplicates the prohibition of their passage through the element ЗИ-НЕ 1 to the input of the direct counting of the reverse binary decimal th to the counters, and 8.

This leads to the fact that the first clocking pulse from the output of the AND element 15 goes through the element 2I-NO 3 to the reversible binary-decimal counter 8 and subtracts one from it, but the binary counter 9 does not add up, since its receipt is blocked -NON 2 zero logic level from output 35 of trigger 14. In addition, at the end of this clocking pulse, trigger 14 (at the D input of logical unit) from the output of trigger 13 switches to one state, which permits the passage of all subsequent pulses from the output element that 15 through the element ZI-NOT 2 for summation into a reversible binary counter 9.

25

thirty

40

one

Thus, due to the NOT 6 trigger, the signal decay, arriving 14, enters binary input 9 at input 17 (transition from a single logic level to zero), the pulse shaper 10 is triggered, the output signal of which records the values of the tetrads into the reversing binary -particular counter 8 and sets in one state trigger 12. This leads to the fact that at the end of the nearest clock pulse received through the element NOT 7 on the C-inputs of the triggers 13 and 14, the trigger 13 is set to one resolves

em is one pulse less than in binary-decimal counter 8. This operation must be performed, since as the signals of the termination

50 transformations use reverse transfer pulses, which are generated in counters 8 and 9 upon receipt of a (t + 1) -th clock pulse, where Hh is the number of clock pulses

55 pulses required to read the converted code from counters 8 or 9. Since (t + 1) -th pulse will be sent to sum up to

five

0

the passage of subsequent clock pulses through the element And 15.

Thus, due to the trigger 13, the start of the conversion process is synchronized with the moment of the clock pulses, which ensures that only the pulses of the same duration pass through the AND 15 element. In addition, the switching of the trigger 13 leads to a change in the information on the D input of the trigger 14. As long as the trigger 14 is in the zero state, the passage of the clock pulses through the NE-NE elements 1 and 2 to the direct count inputs of the reversible counters 8 and 9 is blocked. At the same time, the zero logic level from input 16 prohibits clocking pulses through element 2И-НЕ 4 to the input of the reverse counting of the reversible binary counter 9 and duplicates the prohibition of their passage through the element ЗИ-НЕ 1 to the input of the direct counting of the reverse binary decimal th to the counters, and 8.

This leads to the fact that the first clocking pulse from the output of the AND element 15 goes through the element 2I-NO 3 to the reversible binary-decimal counter 8 and subtracts one from it, but the binary counter 9 does not add up, since its receipt is blocked -NON 2 zero logic level from output 5 of trigger 14. In addition, at the end of this clocking pulse, trigger 14 (at the D input of logical unit) from the output of trigger 13 switches to one state, which permits all subsequent pulses to pass from the output and 15 through the NOT element ZI-2 summation on the reversible binary counter 9.

five

0

0

one

Thus, thanks to trigger 14, binary counter 9 is fed one less pulse than binary to decimal counter 8. This operation must be performed, since as the end signals

transformations use reverse transfer pulses, which are generated in counters 8 and 9 upon receipt of a (t + 1) -th clock pulse, where Hh is the number of clock pulses

pulses needed to read the converted code from counters 8 or 9. Because (t + 1) -th pulse will be sent to sum up to

reversing binary counter 9, then blocking the first of the clock pulses at the input of the direct count of binary counter 9 with a trigger 14 will allow fixing n pulses in it and, therefore, receive the converted code without distortion.

At the end of (tn + 1) -ro clocking pulse, coming from the output of the binary-decimal counter 8 through the element 11 2I (playing the role of the OR element for logical neli) to the C input of the trigger 11, the trigger 12 (on D input logic zero). At the same time, the zero logic level from the trigger output resets to zero and the triggers 13 and 14, which prohibits the passage of the following clock pulses through the element 15. At this point, the process of converting the binary-decimal code to the binary ends, and the code received on output information output 22 is its result

If output 16 is set to a single logic level, then the device can convert the binary code to binary-decimal. The operation of the converter in this mode is similar to that described for the conversion of a binary-decimal code into a binary one, except that the number to be converted is written into a reversible binary counter 9, the first clocking pulse from the output of element 15 is blocked at the input of the direct account of the reversing binary-decimal counter 8, and the result of the conversion is the code obtained at the outputs 20 of the reversible binary-decimal counter 8.

Claims (1)

Invention Formula 4S Reverse binary code converter to binary-decimal core containing reverse binary-decimal and binary counters, first trigger, pulse shaper, 50 first element, whose first input is connected to the converter's clock input, information inputs of binary and binary-decimal codes which is connected to the informational-55 trigger is connected to the third input inputs of the reverse binary and the first and second elements of the ZI-NO.  About 5 20 25 3U o five S 0 binary-decimal counters, respectively, whose outputs are respectively binary and binary-decimal codes and converter 5 outputs, the converter start input is connected to the reset binary and binary-decimal inputs, in order to simplify the converter and expansion of the area of stable operation of the converter, the second and third triggers are entered into it, two elements ZI-NOT, two elements 2I-NOT, BTopoiT element I and three elements NOT, whose inputs are connected respectively to the input p mode, clock input and start input of the converter, the mode input of which is connected to the first inputs of the first elements ZI-NOT and 2I-NOT, the second inputs of which are connected to the output of the first element AND and the first inputs of the second elements 2I-NOT and ZI-NOT, the second inputs which are connected to the output of the first element NOT, the outputs of the first and second elements ZI-NOT are connected respectively to the inputs of the addition of reversible binary-decimal and binary counters, the subtraction inputs of which are connected respectively to the outputs of the second and first elements 2I-NOT, sync-inputs of reversible binary-decimal and binary counters are connected to the output of the pulse former and to the 5-input of the first trigger, whose single output is connected to the D- and R-inputs of the second trigger and to the R-input of the third trigger, the D-input of which is connected to unit output of the second trigger and the second input of the first element, And, C - the inputs of the second and third trigger connected to the output of the second element NOT, and the C input of the first trigger connected to the output of the second element And, the first and second inputs of which are connected to the outputs of the loan reversible binary-decimal and binary counters, respectively, the output of the third element is NOT connected to the input of the pulse shaper and the R-input of the first trigger, D-input of which is connected to the input zero of the converter, the unit output of the third Editor N. Egorova Compiled by M. Arshavsky Tehred L. Oleinik Order 2460/59 Circulation 816 - Subsidiary VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production-printing company, Uzhgorod, st. Project, 4 Proofreader A. Ferenc