SU1545330A1 - Device for monitoring fibonacci p-codes - Google Patents

Abstract

The invention relates to computing and can be used to control information storage and transmission devices operating in sequential Fibonacci codes. The purpose of the invention is to reduce hardware costs. The device contains the shift register 1, the element OR 2, the element AND 3, the trigger 4 and has a new organization of communications. Control about the presence of an error is achieved by the element OR 2 and the element And 3, which allow detecting violations of the minimal form of the sequential P-Fibonacci code. 1 il.

Description

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The invention relates to computing and is intended for use in devices controlling the Fibonacci p-codes.

The aim of the invention is to reduce hardware costs.

The drawing shows a diagram of a device for monitoring p-Fibonacci codes.

The device contains a shift register 1, the element OR 2, the element AND 3, three | - ger, input 5 of the initial installation, information input 6,. informational 7 and control 8 outputs act input 9.

Any natural number A in the n-paraend by the bottom Fibonacci p-code is represented as a polynomial

nZ a,

Ur (t)

where a efoj}

(m) -p is the Fibonacci number (, 1, 2t ... J i

tfp (m) 1 with P

O with n 0,

about;

1 / p (ha-1) 4-cis-p-1),

The method of controlling Fibonacci p-codes for the minimal form is described by the switching function

a, l (a,., wa,. au ... v a ,,), (1)

X where i

n-1, p + 1

The essence of the invention is that the control of the verification condition (the presence of no more than one unit in a group of p + 1 bits) is carried out by means of a consistent knowledge, starting with the higher bits, p + 1 of neighboring information elements according to a logical equation (1 ) with the sequential transmission of Fibonacci p-codes. Thus, the number of control equipment does not depend on the length of the Fibonacci p-code.

The device works as follows.

In the initial state, register 1

the shift and the trigger are set to the zero state by a single signal from input 5.

The binary symbols of the Fibonacci p-code combination, starting with the high-order bits, are input into register 1 from input 6. The lower p-bits of register 1 are fed to the OR 2 element, and (p + 1) are sent to the second.

five

0

five

0

35

40 45

If the first ps of the lower bits of the shift register have a zero value, the output of the OR 2 element and the first input of the AND 3 element will be level zero. The closed element And 3 does not change the zero state of the trigger k.

If one of the p incoming bits to the element OR 2 is one, from the output of the element OR 2 to the first input of the element AND 3 one is received. Then, with the correct code combination (p + 1) - and the bit that arrives at the second input of the element And 3, should be zero, respectively, at the counting input of the trigger C, the signal is also absent. I

If the code combination is wrong, the (p + 1) -and bit arriving at the input of the element AND 3 and the output of the element OR 2 will be one, since there is also a single bit in the group of the lower bits of register 1. Then element 3, a single signal appears that sets the trigger to one. A single signal from the output of trigger 4, signaling the presence of an error in the combination, sets the trigger of register 1 to the zero state.

Younger p-bits of the Fibonacci p-code should always be in the zero state. Therefore, the device receives the ri-p higher bits of the Fibonacci p-code, after which, if an error is not detected, the code combination recorded in register 1 is shifted to the higher bits by the signal from the clock input 9 during the p-slots

Claims (1)

Invention Formula A device for monitoring Fibonacci p-codes containing a shift register, an OR element, an AND element and a trigger, the device information input connected to the information shift register input, the shift resolution input of which is connected to the device clock input, the information and control outputs of which are connected respectively to the output the shift register and with the trigger output the output of the element OR is connected to the first input of the element AND, the input of the initial installation of the device is connected to input 5115 53306 home installation in the On trigger, on the t-second input element And, the output ko; characterized by the fact that it is integrally connected to the counting input reduce hardware costs, you are a trigger, the output of which is connected to the first bit (p + 1) th bit moves, the shift register reset input, the shift register ustregister are connected to the corresponding input of which is connected to the inputs of the OR element and the initial setup of the device.