SU1050125A2 - Bipulse signal receiving device - Google Patents

Abstract

DEVICE FOR RECEPTION OF BIMPULSE SIGNAL on the author. St. N 869072, distinguished by the fact that, in order to improve the accuracy of receiving information, a delay element, an element And and an equivalence element are introduced into it, and the output of the binary counter of clock pulses through the delay element is connected to one input of the element And, the other input is connected to the output of the equivalence element, one input of which is connected to the output of the first trigger, the other input - to the output of the second trigger.

Description

IND

Ate 11 The invention relates to telecommunications and may be used in the construction of discrete information transmission systems. . According to the main author. St. No. 869072 discloses a device for receiving a bi-pulse signal, containing a series-connected limiter amplifier, a bi-pulse signal converter into a telegraph signal and a phase detector with a clock phase auto-tuning unit, a unit for erasing single pulses of a bi-pulse signal connected between the outputs of the amplifier and corresponding inputs of a bi-pulse signal converter into a telegraph signal, with the unit for correcting erasures of single pulses and a pulse signal a contains a two-bit register, the first and second triggers, two irrelevant elements, two keys, two inverters, three OR elements and a binary counter clock-pulses, the output of which is connected to the first inputs of unequalities, the second inputs are connected respectively with the parallel outputs of the two-register-dong register, and the outputs are connected to the control inputs of the first and second keys, with the first output of the first trigger through the first inverter connected in series, the first key and the first OR element, to the second input The second output of the first trigger is connected to the second trigger inputs, the first output of which through the second inverter connected in series is the second key and the second OR element, the second output of which is the first output of the limiter, is connected to the input of the first trigger, and the second and third the output of the second device “transducers” to the input of the converter of the bi-pulse signal 6 is a telegraph signal, and the first and second outputs of the amplifier-limiter are connected to the corresponding inputs1 “AND Tpetbefo of the Element OR The eUx of which is connected to the input of a two-bit register However, in a known device, there is insufficient reception accuracy due to sweeps into a communication rope. A: The purpose of the invention is to increase the accuracy. reception of information. 5J The goal is achieved by having a device. A device for receiving a bi-pulse signal containing a series-connected amplifier-limiter, a converter of a bi-pulse signal into a telegraph signal and a phase detector with a clock-phase control loop, a block for correcting a single pulse of a bi-pulse signal connected between the outputs of the amplifier-limiter and the corresponding inputs of the bi-pulse signal a delay element, an element And, and an element of equivalence are entered into the telegraph signal, with the output of the binary clock counter new impulses through a delay element connected to one input element And the other input of which is connected to the output element of equivalence, one input of which is connected to the output of the first trigger, the other input to the output of the second trigger. The drawing shows a structural electrical circuit of the proposed device. The device contains an amplifier-limiter 1, a block 2 for correcting erasures of a single pulse of a bi-pulse signal, a converter for a bi-pulse signal a and a telegraph signal, a phase detector, a clock phase auto-tuning node 5, block 2 contains a two-digit register 6, the first trigger 7, the second trigger 8, O / 1- - ment 9 and 10 inequalities, keys 11 and 12, inverters 13 and AND, elements OR 15-17 and binary counter 18 clock pulses, the device also contains And 19 element, equivalence element 20 and delay element 21. t. - -. The device operates as follows. :. /. The bi-pulse signal received from the communication channel is fed through the amplifier limiter I to the input of the block "2. For & TOM, the zero pulses of the bi-pulse signal go to the second input of the OR 17 element, and single pulses to the first input of the OR 17 element and to the second input of the OR 16 element and then to the two-digit register 6 of the first and second and second triggers 7 and 8, respectively. The clock pulses are continuously fed to the input of the binary counter 18, the frequency of which is two times higher than the frequency of bi-pulse signals arriving at the input of the amplifier-limiter 1. The binary counter 18 divides into two the frequency of the clock pulses received at its input you're running impulse These inputs are fed to the first inputs of elements 9 and 1J3 of unequalities with controlled outputs, the second inputs of which are signals from the outputs of a two-digit register 6. If erasing a bi-pulse signal. la does not take place, at the output of the amplifier: l-limiter 1 there are two single signals I from each half of the pulse signal) and at the input one of each of the 9 and 10 inequalities with controlled outputs from the output bits of the binary counter output bis .18 arrive,. The peculiarity of the operation of the disparity element with a controlled input is that the signal at its output appears only when there is a signal from the binary counter 18 and no signal coming from the register. With other combinations of input signals, there is no output signal on the Element of unequal 9 with a controlled output. Time delay T k, provided by the element 21. delays, is chosen greater than the time of operation of the chain element 9 (U inequality, key 12 (11), inverter 1 (13) and trigger 8 (7), but less than half the time period of the pulse from the binary counter 18 clock impulses. At the control inputs of the keys 11 and 12. There are no signals and the keys are closed. Suppose that Information enter the input of the proposed device. The distorted signal is written into register 1 by 6 units: in the first discharge and zero in the second, and in triggers 7 and 8 two zeros will be written. At the time of polling elements 9 and 10 An unequal binary counter 18 at the output of element 10 of unequalities causes a signal to open key 11. Information from the first trigger 7 (in this case O) is inverted by inverter 13 and reversed to trigger 8. As a result, trigger triggers 7 and 8 will be information O and 1 are recorded respectively, ie, the erased pulse will be recovered. Delay element 21 ensures the arrival of pulses from the output of the binary counter 18 clock pulses with the above delay, therefore: im1 54 pulse to the second input of the element 19 And enters e than occurs correction information triggerah.Takim manner, when an example situation, resulting in the appearance of boiling. in triggers 7 and 8 simultaneously of two information zeros, the signal fails due to the fact that the pulse from the output of the binary counter 18 clock pulses to the second input of the element I 19 comes later than the correction of the information occurred. This leads to the fact that the signals received previously, trigger outputs 7 and 8 and the triggering equivalence element 20, which ensured the presence of a signal at the first input of element 19, were removed before the second input of element 19 had a signal from the output of delay element 21. The delay element 21 of the delay a is chosen from the above considerations, then a signal of failure at the output of the element 19 is not generated in the case under consideration. The device works in a similar way when restoring any erased pulse, except for the case when the very first pulse in a given parcel is erased. V. dan case. In addition, information is provided by the device starting from the second pulse, as a result of which the signal conversion is performed with inversion. At the time of the change of the transmitted symbol (for example, the transition from transfer 1 and transfer O), two units will be recorded in register 6, and in triggers 7 and B two zeros will be written. At the same time, at the controlled outputs of the inequality elements, signals do not appear, keys 11 and 12 remain closed, and the correction of information in the triggers 7 and 8 does not occur. Thus, according to the signals from the outputs of the triggers 7 and 8, the element ekv triggers 20 and triggers a signal to the first input of the element And, 19. When this element arrives at the second input, a pulse from the output of delay element 21 at the output of the element 19 And 193 shows the signal Failure which is used to stop the processing of a given parcel and generate: request and receive a new parcel from the transmitting device. Technical and economic effect (Is to improve the performance of the device 51050

increasing the ability to detect interference and increasing the speed of receiving information with the presence of interference in the communication channel.

-. five

The proposed device, unlike the base object - bi-pulse modem BIM-032 HD2.081.032 - allows -.

Before converting the bi-pulse signal into a telegraph signal, it is possible to detect the disappearance of the first pulse of the parcel and give a signal of failure immediately upon transition from reception O to reception 1, or vice versa. As a result, measures will be taken to repeat the package. .

Claims (1)

DEVICE FOR RECEIVING A BI-PULSE SIGNAL by ed. St. No. 869072, characterized in that, in order to improve the accuracy of receiving information, a delay element, an AND element, and an equivalence element are introduced into it, the output of the binary clock counter through the delay element being connected to one input of the And element, the input of which is connected to another with the output of the equivalence element, one input of which is connected to the output of the first trigger, the other input - with the output of the second trigger. bo SL> The goal is achieved by the fact that the device. a device for receiving a bi-pulse signal, containing a serially connected amplifier-limiter, a converter of the bi-pulse signal to a telegraph signal, and a phase detector with a phase-locked loop, a correction unit for erasing single pulses of a bi-pulse signal connected between the outputs of the amplifier-limiter and the corresponding inputs of the bi-pulse signal converter in the telegraph signal, a delay element, an AND element, and an equivalence element are introduced, and the output of a binary clock counter of pulses through the delay element is connected to one input of the AND element, the other input of which is connected to the output of the equivalence element, one input of which is connected to the output of the first trigger, and the other input with the output of the second trigger. The drawing shows the structures. naya electric circuit of the proposed device. The device contains a limiter amplifier 1, a unit 2 for correcting erasures of single pulses of a bi-pulse signal, a converter 3 of a bi-pulse signal to a telegraph signal, a phase detector 4, a phase-locked loop 5, block 2 contains a two-bit register 6, the first trigger 7, the second trigger 8, ede- ~~ ment 9 and 10 of disambiguation, keys 11 and 12, inverters 13 and 14 OR output I