SU1088144A1 - Bipulse signal receiver - Google Patents

Abstract

A BIMPULAR SIGNAL RECEIVER containing a series-connected stand-by multivibrator and the first differentiating unit, as well as the second and third differentiating units, the first and second memory block, and the pulse shaper, whose output is the clock output of the bi-pulse signal receiver, characterized by the fact that increase noise immunity; the first bi-pulse signal converter into a single-pulse signal, an additional multivibrator and the first An OR, a second bi-pulse signal converter into a single-pulse signal, a second OR element and a decision block, the first and second inputs of the decision block are connected respectively to the outputs of the first and second memory blocks, the combined clock inputs of which are connected to the outputs of the second OR element, the output of the first bi-pulse signal converter into a single-pulse signal is connected to the information input of the first memory block; the output of the second bin-pulse signal converter in. monopulse signal - to the information input of the second memory block and the input of the waiting multivibrator, the output of which is connected to another input of the first OR element, the output of which through the second differentiating unit is connected to the first input of the second SHSh element, the second and third inputs of which are connected respectively to the outputs of the first the differentiating unit and the third differentiating unit, the input of which is connected to the output of the additional standby multivibrator, and the output of the second element OR is connected to the input of the forms The detector 00 CX). Tactical pulses, while the combined inputs of the first and second bi-pulse signal converters into a single-pulse signal are input 4; the home of the bi-pulse receiver, and the output of the decision block is the output of the bi-pulse receiver.

Description

The invention relates to telecommunications and can be used in data transmission. A bi-pulse receiver contains a series-connected amplifier-limiter, a bi-pulse signal converter into a telegraph signal and a phase detector, as well as a clock frequency auto-tuning unit, the input and output of which are connected respectively to the output of the bi-pulse signal converter into a telegraph signal and another phase input detector The closest in technical essence to the invention is a bi-pulse signal receiver containing series-connected waiting The libator and the first differential block, as well as the second and third differential blocks, the first and second memory blocks and the driver are also pulsed, the output of which is the clock output of the receiver of the pulse signal, the first output of the standby multivibrator through the second differentiating block connected to the input of the first memory unit, the second output of the standby multivibrator through the pulse shaper and the third differentiating unit connected to the input of the second memory unit, the output of which through the comparison unit is It is connected to another input of the first memory block, and the input of the first differentiating unit is combined with other inputs of the second memory unit and comparison unit W. A disadvantage of known bi-pulse signal receivers is low noise immunity in the presence of erasures and inserts in the communication channel. The purpose of the invention is to improve noise immunity in the presence of erasures and inserts in the communication channel. To achieve this goal, a bi-pulse signal receiver containing successively connected pending multivibrator and the first differentiating unit, as well as the second and third differentiation blocks, the first and second memory blocks and the clock pulse generator, the output of which is the clock output of the bi-pulse signal receiver, are entered serially connected first biopulse signal to monopulse signal converter; additional standby multivibrator and first OR element, as well as the second A bi-pulse signal generator, a mono-pulse signal, a second OR element and a decision block, the first and second inputs of the decision block are connected respectively to the outputs of the first and second memory blocks, the combined clock inputs of which are connected to the outputs of the second OR element, the output of the first bi-pulse signal to the monopulse signal is connected to the information input of the first memory block, the output of the second converter of the biopulse signal into the monopulse signal is connected to the information input the second the memory unit and the standby multivibrator input, the output of which is connected to another input of the first OR element, the output of which is connected to the first input of the second ShZh element through the second differentiating unit, the second and third inputs of which are connected to the outputs of the first differentiating unit and the third differentiating unit, respectively whose input is connected to the output of an additional standby multivibrator, and the output of the second element OR is connected to the input of the clock generator, with the combined inputs n the first- and second signal converters biimpulsnogo monopulse signal are input biimpulsnogo receiver signal, and an output unit reshakvtsego is biimpulsnogo receiver output signal. The drawing shows a structural electrical circuit of a bi-pulse signal receiver. The bi-pulse signal receiver contains the first and second converters 1 and 2 of the bi-pulse signal into a mono-pulse signal, stand-by multivibrator 3, additional stand-by multivibrator 4, first and second differentiating units 5 and 6, third differentiating unit 7, first and second elegents OR 8 and 9, first and the second memory blocks 10 and 11, the decision block 12 and the generator of 13 clock pulses. The receiver bi-pulse signal works as follows. The information encoded in the bi-pulse signal is fed to the combined inputs of the first converter 1 and the second converter 2, which convert the bipolar signal into mono-pulse signals corresponding to each polarity of the nxA signal. Monopulse signals arrive at the information inputs of the first and second memory blocks 10 and 11 and the inputs of the waiting multivibrator 3 and the additional waiting multivibrator 4. The waiting multivibrator 3 and the additional waiting multivibrator 4 are triggered by the leading edge of the pulses arriving at their inputs, and the duration of the pulse forming them is em 0.75 T, where T is the period of the following pulses. The signals from the outputs of the standby multivibrator 3 and additional loduscheg multivibrator 4 are received through the first element OR 8 and the second differentiating unit 6 to the first input of the second element OR 9, the second and third inputs of which receive signals from the outputs of the first differentiating unit 5 and the third differentiating unit 7, respectively The pulse sequence from the output of the second element of the LI 9 is fed to the clock inputs of the first and second blocks 10 and 11 of the memory, made in the form of four-bit shift registers. The output signals of the bits of the first and second blocks 10 and 11 of the memory are received respectively on the first

and the second inputs of the decision block 12, in which the initial information is determined by comparing the information recorded in the two-adjacent cycles. In this case, if the sum modulo two bit information in the first and fourth bits of the shift registers of the first 10 or second 11 memory blocks is 1, then the received information is 1, and otherwise - O. In the case of erasing information or the appearance of new impulses (inserts) no more than one distortion lasting half the clock interval over an interval of two clock intervals of distortion of the input signals are determined by a decisive block of 12 In the latter, the modulo two of the first and second shift registers are implemented blocks 10 and 11 of memory. If this sum is equal to 1, then this channel (for example, the first converter 1 connected in series and the first memory block 10) receives information with an error and information from the second channel is received (the second converter 2 is connected in series with the second channel). memory block 11).

In this way, the initial information is recovered from the received signals when they are distorted by erasers and inserts.

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Claims (1)

BI-PULSE SIGNAL RECEIVER, comprising a series-connected standby multivibrator and a first differentiating block, as well as a second and third differentiating blocks, a first and second memory block and a clock driver, the output of which is a clock output of a bi-pulse signal receiver, which is characterized by the fact that, in order to increase noise immunity, the first converter of the bi-pulse signal into a monopulse signal, an additional standby multivibrator and the first electronic an OR element, as well as a second converter of a bi-pulse signal into a single-pulse signal, a second OR element and a decision block, while the first and second inputs of the decision block are connected respectively to the outputs of the first and second memory blocks, the combined clock inputs of which are connected to the outputs of the second OR element , the output of the first bi-pulse signal to mono pulse signal converter is connected to the information input of the first memory block, the output of the second bi-pulse signal converter c. monopulse signal - to the information input of the second memory block and the input of the standby multivibrator, the output of which is connected to another input of the first OR element, the output of which through the second differentiating unit is connected to the first input of the second OR element, the second and third inputs of which are connected respectively to the outputs of the first differentiating block and the third differentiating block, the input of which is connected to the output of an additional standby multivibrator, and the output of the second OR element is connected to the input of the formative For clock pulses, the combined inputs of the first and second converters of the bi-pulse signal to the single-pulse signal ° are the input of the receiver of the bi-pulse signal, and the output of the decision block is the output of the receiver of the bi-pulse signal. 3>