SU1218489A1 - Device for transmission and reception of binary digital information - Google Patents

Abstract

The invention relates to the field of telecommunications and can be used to transmit data: in digital computers, phototelegraphy and telemetry. The goal is to increase bandwidth. The device contains on the transmitting side - a switch 1, an output matching unit 2, an operational amplifier (Oyj 3, data storage unit 4, timing pulses 5, a frequency divider by two 6, elts 2I 7,8,12,13, counting triggers (CT) 9.11, at the reception room C /) F (/ 1

Description

to the side - a synchronous trigger 14, a detector (D 15, delay delay 16, input matching unit 17, amplitude limiter 18, shaper of short pulses 19. The signal generated for transmission on. - does not contain a single communication line in the spectrum DC with any combination of information symbols O and I. It is also possible to transmit DC for power

The invention relates to telecommunications and can be used for data transmission in digital computer systems, phototelegraphy and telemetry.

The purpose of the invention is to increase throughput.

FIG. Figure 1 shows the structural: electrical circuit of the proposed device; figure 2 - timing diagrams.

The proposed device for transmitting and receiving binary discrete information contains on the transmitter side a switch 1, an output matching unit 2, an operational amplifier 3, a data storage unit 4, a generator of 5 timing pulses, a frequency divider 6 into two, the first 7 and the second 8 elements 2I, the first counting trigger 9, element 2ILI-NOT 10, the second counting trigger 11, the third 12 and fourth 13 elements 2I, on the receiving side - synchronous trigger 14, detector 15, delay element 16, input matching unit 17, amplitude limiter 18, driver 19 short pulses.

The device works as follows.

When the power is turned on (power lines are not shown), the triggers 9, 11 and 14 are reset to zero states. A digital word is stored in the data storage unit (operative memory, permanent memory, data register), which must be transmitted via a communication line, for example 01011100. The generator 5 of the timing pulses generates directors. This signal has a high noise immunity, because it contains error protection (units are alternated by polarity). The proposed device allows increasing the bandwidth of a communication channel with a limited bandwidth by 1.8 times. The goal is achieved by the introduction of CT 11, elekt-2I 12, 13, OUZ, switch 1, el-delay 16 and D15. 2 Il.

carbon pulses with a frequency ig (figure 2, a), necessary to synchronize the selected data rate. If on a single output

of the data storage unit 4 there is a logical O, and on the inverse, therefore, 1, the pulse with frequency ij passes through the first element 2 and 7 (FIG. 2, 6), the element 2, OR NOT 10

(Fig.2, c) and further - to the output matching unit, as well as to the input of the sample of the data storage unit 4. On the falling edge of the inverted pulse, the second counting switch is switched

trigger 11 (FIG. 2 d), and the data storage block 4 counts the next bit of information on the increasing front of this pulse. If logical 1 appeared at its unit code, then the next pulse from generator 5

the timing pulses pass through the second element 2 and 8. The first counting trigger 9 is established on the falling edge of the first pulse.

in the unit state and on the falling edge of the second pulse is set to the initial state.

Thus, if logical 1 is present at the unit output of data storage unit 4, then the second element 2 and 8 transmits two pulses from the generator 5 clock pulses, and the first counting trigger 9 generates one double pulse, which also passes through the element 2IL-NOT 10. This doubled and inverting impulse is similar to the previous one, the second counting trigger 11 is switched (Fig. 2, d), and the storage unit 4

Data reads the next bit of information. Secondly, the counting trigger II, the third 12 and the fourth 13 elements 2I and the operational amplifier 3 form a bipolar discrete signal (FIG. 2, e) with a ratio of periods T 2T with constant squaliness, while the signal element with period Tj corresponds to one bit of information - logical 1, and Tj - logical o. This signal in the output matching unit 2 passes through a low-pass filter (LPF) and, after amplification, is transmitted over the communication line. LPF (not shown) in the output matching unit 2 is calculated so that the cutoff frequency of the filter bit is equal to

"one

wed

T, t. equal to the frequency of the larger pulse (logical 1), and the pulses with a frequency of 1/12 corresponding to a logical o fall into the attenuation band of the filter, for example, with a slope of 12 dB per octave. All higher harmonics must be in the lowpass filter.

At the receiving side, the signal enters the input matching unit 17, where it is amplified by the amount of attenuation in the communication line and filtered out of the interference of FIG. 2, g). A detector 15, implemented in an amplitude discriminator circuit with an adjustable response threshold, converts the signal into a video signal (Fig. 2, g), which is then fed to the first (informational) input of the synchronous trigger 14. In the amplitude limiter 18, the signal is aligned with. the amplitude, and in the shaper 19 of short pulses, when the signal passes through the zero level, pulses are formed by the differentiating circuit (Fig. 2, and, the delay element 16 shifts them by a fixed value T so that the switching of the synchronous trigger 14 is important at an extreme signal value, corresponding to logical 1 (FIG. 2, K.) This achieves a high reliability of the synchronous trigger 14, which is recovered; there is an information signal (figure 2, g, l) i The signal used in the described device has p rectangular range sinx / x, wherein

18489

the constant component is also contained. If this link is used to transmit the power of a direct current, for example, in coaxial single-wire lines for powering transmitter circuits without access, the separation of the signal is difficult. For such devices, several different waveforms are offered,

10 provides a simple separation of the information signal, since it no longer contains a constant component. In this case, the information bit O is transmitted as O. The primary side remains unchanged, and in the transmitting side, switch 1 is set to position P and doubled pulses with frequency ig / 2 are received from the generator 5 of the clock 5 to the input of the data storage unit 4. pulses through a frequency divider 6 for two, The rest of the block diagram of the device operates in a similar way. The signal thus generated for transmission on a single link does not contain a constant component in the spectrum for any. combinations of information symbols O and 1.

Therefore, at the same line, direct current can be transmitted to power the elements, for example, a remote antenna array in sonar. Such a signal has a high noise immunity, since it contains properties of error protection (units always alternate in polarity).

The proposed device for transmitting and receiving binary discrete information allows increasing the bandwidth of a communication channel with a limited bandwidth by 1.8 times compared with the known

device. 45

Claims (1)

Invention Formula A device for transmitting and receiving binary discrete information, co50 holding on the transmitting side the generator of timing pulses, the output of which is connected to the input of a frequency divider by two, with the first input of the first element 2I and with the first input 55 of the second element 2I, the second input of which is connected to the unit output of the data storage unit, the inverse output-: the course of which is connected to the second input the house of the first element 2I, the output of which is connected to the first input of the element 2Ш1И-НЕ, and the output matching unit, and on the receiving side a synchronous trigger, the input matching lean unit whose output through the amplitude limiter is connected to the input of the short pulse shaper, characterized in that , in order to increase the bandwidth, two counting flip-flops, the third and fourth elements 2И, are inserted into the transmitting side; the operational amplifier and the switch, the per- for1 switch, is connected to the input of the storage unit, the second output of the switch is connected to the output of the frequency divider by two, the output of the second element 2I is connected to the input of the first counting trigger, the output of which is connected to the second input of the elea 1 about 1 1 1 00 2ILI NOT, whose output is connected to the third output of the switch, to the first inputs of the third and the fourth elements 2I and to the input is a second of the counting trigger, the unit and inverse outputs of which are connected to the second inputs of the third and fourth elements of the 2I, respectively, whose outputs are connected to the outputs of the operational amplifier, the output of which is connected to the input of the output matching unit, and are entered on the receiving side element delay and detector, the output of which is connected to the first input of the synchronous trigger, the second input of which is connected to the output of the delay element, the input of which is connected to the input shaper short pulses, while the output of the input matching unit is connected to the input of the detector. FIG. 2 Compiled by V. Chibisov Editor N. Shvyschka Tehred T. Tulik Proofreader E. Sirohman Order 1139/61 Circulation 624 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 4/5, Moscow, Zh-35, Raushsk nab. 4/5, Moscow Branch PPP Patent, Uzhgorod, st. Project, 4