SU1185627A1 - Device for synchronizing multifrequency signal receiver - Google Patents

Abstract

1. A SYNCHRONIZATION DEVICE for a MULTI-FREQUENCY SIGNAL RECEIVER, containing a series-connected clock, a first addition-exclusion unit, a frequency divider, a second addition-exclusion unit and a ring register, a low-pass filter sequentially connected, and an analog-digital converter, as well as an adder, and N signal processing channels, each of which consists of a serially connected demodulator, receive filter, square pulse shaper, and differential cue block, negative pulse selector and single pulse generator, the outputs of the analog-digital converter are connected to the corresponding control inputs of the first pulse suppression block, the combined inputs of the demodulators being the input of the device, and the outputs of the ring register are the outputs of the device differing from that, in order to extend the functionality by providing synchronization in multi-channel communication systems with multi-position signals, introduced The first element OR and the RS trigger, as well as the second element OR, M – 1 of the chains, are each connected in series. Yes, of which consists of a series-connected additional adder and a threshold block, an additional threshold block, a mismatch signal generator and H circuits, each of which consists of a series-connected And element and an additional low-pass filter, and each channel. signal processing signals are connected in series with the signal detector and shift register, when (the RS trigger output is connected to the input of the low-pass filter, the output of the frequency divider is connected to the R input of the RS trigger and the combined clock inputs of the shift registers and signal detectors N channels, signal processing, in each of which informational input, you find a 100 L signal connected to the trout output of a rectangular pulse generator, Od outputs of single pulse drivers of N signal processing channels sl are connected to the inputs of the first ISH element, the outputs of the signal detectors and shift registers of the N signal processing channels are connected to the corresponding inputs of the switch, the outputs of which are connected to the inputs of the adder and additional adders, the outputs of the threshold blocks and the additional threshold block are connected to the inputs of the second OR element, whose output connected to the combined first inputs of the elements And, the second inputs of the elements And the connection

Description

chips to the corresponding colts-1m outputs of the collioRot register, the outputs of the additional low-pass filters are connected to the corresponding inputs of the error signal generator, the outputs of which are connected to the corresponding control inputs of the second pulse addition and exclusion unit, and the output of the adder is connected to the input of the additional threshold block.

2. The device according to claim 1, characterized in that the misalignment driver is made in the form of an N-1 decoder

comparators, with each j-th block of comparators (J 1, 2, ... N-1) consisting of N - j comparators, the outputs of which are connected to the corresponding inputs of the decoder, the direct inputs of the comparators of each j-ro block of the comparators are combined and connected to the inverting inputs of the respective comparators of the j-1 comparators, the combined direct inputs of the comparators of each j-th comparators block are the inputs of the error generator, and the outputs of the decoders are the outputs of the error signal generator.

The invention relates to the synchronization of multi-channel communication systems with multi-frequency composite BID signals of a time-frequency matrix for transmitting discrete messages over multipath channels of radio waves and can be used in receivers of discrete signals of a time-frequency matrix type.

The aim of the invention is to extend the functionality by providing synchronization in multi-channel communication systems with multi-position signals.

FIG. Figure 1 shows the structural electrical circuitry of the synchronization device of the receiver of multi-frequency signals; in fig. 2 is a structural electrical circuit of a mismatch signal generator.

The synchronization device of the receiver of multi-frequency signals contains N channels of signal processing 1, the first element OR 2, R5-trigger 3, low-pass filter 4, analog-to-digital converter (ADC) 5, generator 6 clock pulses, the first block of addition-removal of pulses 7, divisor 8 frequencies, the second unit for adding and excluding pulses 9, the ring register 10, the switch 11, the adder 12, the M-1 additional adders 13, the M-1 threshold blocks 14, a dogtop threshold block 15,

the second element OR 16, N elements AND 17, N of additional low-pass filters 18, a driver 19 for the error signal.

Each of the N channels of signal processing 1 contains a demodulator 20, a receive filter 21, a shaper 22 of rectangular pulses, a differentiating unit 23, a negative pulse selector 24, a shaper

25 single pulses, signal detector 26, shift register 27.

The error signal generator 19 comprises N (N-1) / 2 comparators 28 and a decoder 29.

The device synchronization receiver multifrequency signals works as follows.

To the input of the synchronization device of the receiver of multi-frequency signals comes a multi-frequency multi-position signal of the form of a sequence of frequency-time arrays (CTM)

(Fig. 1). The group signal is a sequence of radio pulses at different frequencies (, fjj J p), shifted in time by the interval t (t),

where T is the duration of the group signal. In this example of the technical implementation of the proposed synchronization device of a multi-frequency signal receiver, an optimal ensemble of multi3 positional multi-frequency signals (MES) with the number of elements (frequencies) equal to N 5 and including M 4 time-frequency arrays is used. The initial phase of each of the channel FM radio pulses can be manipulated (in phase) by Ji. In each of the N channels of signal processing, the demodulator 20 and the filter 21 are either amplitude (in this case, the demodulator 20 is implemented as an amplitude detector) or phase (in this case, the demodulator 20 is implemented as an interceptor and a motor). coherent signal) detection of the signal transmitted over a given frequency. The frequency band of the filter 21 is consistent with the duration of the V elementary channel signal shaper 22 provides the detected pulses to one (positive) polarity (if the channel signals are phase-shifted) and provides for the formation of rectangular pulses whose duration is equal to the duration of the corresponding radio pulses. The differentiating unit 23 forms peaked pulses of different polarity corresponding to the leading and falling edges of the input pulse sequence. . The selector 24 provides for the emission of negative pulses. The pulse sequences formed by the formers of 25 N signal processing channels 1 are combined using the first element OR 2. The formers 25 form pulses of short duration and with the nominal levels necessary to trigger the R5 trigger 3 and through the 5th input. The pulses of this sequence set the R5 thrigger 3 to the state 1. The setting of the short-circuit trigger 3 to the state O is produced by a sequence of pulses with a frequency Rc 1 / f, coming from the output of the frequency divider 8. This pulse sequence arrives at the R-input of RS-flip-flop 3. At the output of RS-flip-flop 3, pulses appear with a duration proportional to the time difference of the pulse signal at the output of frequency divider 8 relative to the input signal of the CWM. The duration of these 274 pulses can vary from 0 to t, where the duration of one frequency element is CVM. As a result of the action of noise and multipath propagation medium, the pulse duration at the output of the RS flip-flop 3 takes the value and V V, where 1 Gfd is the fluctuating duration; TCP is the mathematical expectation of a random variable Tf,. Using filter 4, the DC component of the pulse signal is selected. This provides filtering of the noise component. The voltage at the output of the filter 4 carries information about the averaged (over all parallel frequency i processing branches) temporal mismatch of the input signals of the CWM (times of frequency change) relative to the pulse signal generated at the output of the frequency divider 8. Constant voltage at the output The filter 4 is accurate to the noise component where A is the amplitude of the pulses at the output of the 5.-trigger 3. The maximum value of C is A - (at tcp f) the minimum value of I is U / (at T, - O, t. in the absence of asynchronism two compares the signal pulses). A constant voltage from the output of the filter 4 is supplied to the ASCH1 5 of continuous operation with information in the parallel code about the level of the constant component at the output of the filter 4. Digital signals from the outputs of the A / D converter 5 are fed to the corresponding control inputs of the first pulse addition-exclusion unit 7 which is intended for fine tuning of the phase synchronization system with the LT / T / K step, with 2 7 k, where n is the number of outputs (bits) of the ADC 5, and V is the division factor of 8. 8. The principle of the phase adjustment is as follows. The generator 6 produces a sequence of short pulses with a frequency F. k / t. depending on the value of the logic signal at the outputs of the A / D converter 5 in the first block of addition-deactivation of pulses 7 or a certain number of pulses is subtracted, thereby reducing the phase, the libr adds a certain number of pulses to increase the phase. As a result of subtracting or adding a single pulse, the phase of the output pulses of the divider 8 varies in duration by LT. Thus, at the output of divider 8, a sequence of pulses is formed (with a tracking frequency F, 1 / jr), which is synchronous (with an accuracy of up to) with time boundaries frequency elements of the MES regardless of the type of input signals. This sequence is fed to the signal input of the second addition-exclusion unit 9, to the control inputs of which is fed the r-bit () digital control signal nor (in parallel code) generated by the shaper 19. The operation of the second pulse addition adding unit 9 is similar to the operation of the first pulse addition-deletion unit of 7. W. a swarm of pulses 9 from the incoming pulse sequence (from divider 8) subtracts or adds L pulses (depending on the value of the signal at the generator 19 outputs) where L is the digit code at the generator 19 outputs. This ensures the change in the number of forward pulses of the ring register 10, and thus the time shift of the synchronization pulses at the outputs of the ring register 10 by the value of 4Т. The formation of the control signal of the incoming to the control inputs of the additional control block 17, the second pulse addition adding unit is performed as follows. The pulse signal from the output of the generator 22 of each signal processing channel 1 is fed to the input of the signal detector 26, the clock input of which is supplied with a clock signal from the code of the divider 9. Detector b. The signal 26 detects the signal transmitted to a given frequency, and generates a sequence of rectangular pulses with a duration T at its output. The temporal boundaries of these pulses are synchronized with the sync signal from the output of the divider 8. , the threshold block and the RS flip-flop, and the integrator input, as well as the integrated clock inputs of the integrator, the threshold block and the R input of the Trigger 3 are respectively, the information and clock inputs of the signal detector 26, and the direct output of the RS flip-flop 3 is the output of the signal detector 26, the pulse sequence from the output of the signal detector 26 (each of the N channels of signal processing 1) is fed to the signal input of the shift register 27 (consisting of N-1 bits), which serves as a discrete delay line. To ensure the synchronous operation of the shift registers 27 of the N signal processing channels 1, the clock inputs of the shift registers 27 receive the clock signal from divider 8. The pulse sequences from the outputs of the signal detectors 26 and the delayed sequences from the outputs of the shift registers 27 of the signal processing channels 1 are fed to the corresponding inputs switch 11. The latter has NN inputs and outputs (where M is the number of CVMs in the signal ensemble). The switch 11, in accordance with the structure of the ensemble of multi-position MES used, provides the connection of the corresponding inputs to the corresponding outputs. The corresponding outputs of the switch 11 are connected by a circuit consisting of series-connected adder 12 and an additional threshold unit 15 and M-1 circuits, consisting of series-connected additional adders 13 and threshold units 14. Pulse sequences formed at the outputs of the additional threshold unit 15 and threshold-, blocks 14 are combined by the second element OR 16. The temporal position of the pulses of this signal carries in itself information about the time limits of the received MES (borders of the CWM). The pulse sequence from the output of the second element OR 16 arrives at the combined first inputs of the elements AND 17, the second inputs of which receive the sync signals from the corresponding outputs of the ring register 10. The purpose of the elements 17 and 17 of the additional filters 18 and the former 19 is: to determine whether the temporary position corresponds to a pulse signal at the output of the second element OR 16 time boundaries of the pulse sequence at the outputs of the ring register 10 and generate a control signal that is fed to the control the input inputs of the second pulse elimination addition unit 9. The voltages from the outputs N additional: filters 18 are fed to the inputs of the former 19. These voltages will be of a greater magnitude, with the greater number of pulses 27 entering the input of the corresponding additional filter 18. The former 19 2) works as follows. The DC voltages generated by 1 additional filters 18 are compared with each other using comparators 28, the outputs of which generate a logical signal .1, if the voltage supplied to the direct input of the comparator 28 is greater than the input to the inverting input, Otherwise, a signal O is generated. For the case when pulse sequences are formed at the output of the ring register 10, logical signals (O or G) will be generated at the output of the comparators 28. The state of the outputs of the comparators 28 is decrypted using a decoder 29, the outputs of which form a digital signal in a parallel code. This signal is fed to the control inputs of the second unit for adding and excluding pulses 9.

FIG. Z

Claims (2)

1. MULTIFREQUENCY SIGNAL RECEIVER SYNCHRONIZATION DEVICE, comprising a series-connected clock generator, a first pulse add-exclude unit, a frequency divider, a second pulse add-exclude unit and a ring register, a low-pass filter and an analog-to-digital converter, as well as an adder, connected in series and N signal processing channels, each of which consists of a series-connected demodulator, a reception filter, a rectangular pulse shaper, differentiating of the block, the negative pulse selector and the unit of single pulses, the outputs of the analog-to-digital converter are connected to the corresponding control inputs of the first block of adding pulse elimination, and the combined inputs of the demodulators are the input of the device, and the outputs of the ring register are the outputs of the device, characterized in that, for the purpose of, expanding functionality by providing synchronization in multi-channel communication systems with multi-position signals, the following the first OR element and the RS-trigger, as well as the second OR element, M-1 circuits, each. giving of which consists of sequentially connected an additional adder and a threshold block, an additional threshold block, a driver of the error signal and N circuits, each of which consists of a series-connected element And and an additional low-pass filter, and in each of the channels. the signal processing A signal generator and a shift register, while the output of the RS-trigger is connected to the input of the low-pass filter, the output of the frequency divider is connected to the R-input of the RS-trigger and the combined clock inputs of the shift registers and signal detectors of N channels, signal processing, in each of which -, the information input of the signal detector is connected to the output of the rectangular pulse shaper, the outputs of the single pulse shapers of the N signal processing channels are connected to the inputs of the first OR element, the outputs of the signal detectors and registers the shift of N signal processing channels are connected to the corresponding inputs of the switch, the outputs of which are connected to the inputs of the adder and additional adders, the outputs of the threshold blocks and the additional threshold block are connected to the inputs of the second OR element, the output of which is connected to the combined first inputs of the AND elements, the second inputs of the elements AND connect SU,. ,, 1185627 1 185627 are connected to the corresponding outputs of the circular register, the outputs of the additional low-pass filters are connected to the corresponding inputs of the mismatch signal generator, the outputs of which are connected to the corresponding control inputs of the second pulse add-exclude block, and the adder output is connected to the input of the additional threshold block. 2. The device according to p. 1, characterized in that the driver of the error signal is made in the form of a decoder N - 1 blocks of comparators, and each j-th block of comparators (J = 1, 2, ... N-1) consists of N - j comparators, the outputs of which are connected to the corresponding inputs of the decoder, the direct inputs of the comparators of each j-ro block of comparators are combined and connected to the inverting inputs of the corresponding comparators of j-1 blocks of comparators, and the combined direct inputs of the comparators of each j-th block of comparators are inputs of mismatch signal generator, and the outputs of the decoders are the outputs of the mismatch signal generator.