SU1506566A2 - Discrete information transmission system - Google Patents

Abstract

This invention relates to a multi-channel radio relay. The purpose of the invention is to increase noise immunity by reducing the effect of clock jitter. Introduction on the transmitting side of the pulse generator and four blocks of coincidence provides the phase change of the frequency-manipulated signal with a minimum shift of 0, ϕ / 2, ϕ, 3ϕ / 2 over the time interval T ₁ less _{than the} duration of the clock interval of the transmitted digital signal, and thereby increases the area of maximum opening the eyes of the diagrams at the inputs of the solvers, practically excluding the effect of the clock jitter on the noise immunity. 2 Il.

Description

The invention relates to a multichannel radio relay communication, may find application in the construction of discrete information transmission systems. and is an improvement of the invention on author. St. No. 1262741.

The aim of the invention is to increase noise immunity by reducing the effect of clock jitter.

 Figure 1 shows the structural-electrical circuit diagram of the transmitting side of the system; figure 2 - the same, the receiving side of the system.

The system contains on the transmitting side a source 1 of the service communication signals, a source 2 of discrete information, a synchronization unit 3, a first counter 4, an inverter 5, a generator 6 of a sync signal of code groups

linear sync shaper 7, shift block B, sequential register 9, parallel register 10, memory block 11, prohibition block 12, code base converter 13, second counter 14, frequency modulator 15, high-pass filter 16, block 17 gating, the first adder 18, the second adder 19, the driver of the pulses 20 and the blocks 21 - 24 coincidence, and on the receiving side. non-receiver 25 of service signaling signals, receiver of discrete information 26, binary signal generator 27, information packet boundary recovery unit 28, intermediate frequency amplifier 29, correlation receiver 30, code base inverter 31, first decision unit 32, second decisive

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block 33, block 34 for restoring the boundaries of linear parcels, decoder 35, block 36 for restoring the boundaries of code groups, block 37 for monitoring, recorder 38 for errors, the correlating receiver 30 containing multipliers 39 and 40, controlled phase shifter 41, driver 42 an error signal, a delay element 43, integrators 44 and 45, low-pass filters 46 and 47, phase shifters 48 and 49, and a selection unit 50, and the error recorder 38 contains a counter 51 and an indication unit 52.

The system works as follows.

The conversion of a binary base to a quad is performed in accordance with the following table.

35

45

In the table next to each quaternary code group: the value of the digital sum in this group is calculated, calculated as the algebraic sum of the amplitudes of the pulses in the code group under the condition that the normalized voltage -1 is assigned to the symbols O, 1,2, and 3 Q code ,five; -0.5; +0.5; +1.5

Above each of the three columns of code groups is the value of the digital sum at the boundary of code groups stored in memory block 11 on the transmitting side by the time the next binary group consisting of three characters arrives from source 2 output of discrete information synchronized by block 3 synchronization, and recorded in the serial register 9 inverse binary clock frequency

from the output of the inverter 5. The three characters recorded in the serial register 9 are rewritten by the Inverse code clock signal from the second output of the driver 6 of the code clock signal

55

0

five

0

five

five

Q

five

groups in parallel register 10 and stored there for a time of three binary clock intervals. The second group of inputs of the converter 13 base code from the output of the memory block 11 receives the value

the preceding digital sum on the border of code groups, represented in binary form, and the first input is a code sync signal from the first output of the imaging unit 6, which is also fed through the imaging unit 7 and block 8 to the first counter 4. Moreover, the zero in the code sync signal corresponds to the first quater character the output of the Converter 13, and the unit is the second. The four outputs of converter 13 are symbol bus 0, 1.2, and 3. Thus, if (corresponds to signal 100 at the output of memory block 11), according to the table, the incoming binary group, for example 011, is encoded by the group from the left column of the table , in this case, 32, which at the output of the first adder 18 is represented by two pulses with amplitudes of +1.5 and +0.5 and duration T, with T, where T is the period of the horizontal signal. The duration of the pulses Tj is formed by the pulse shaper 20 and the matching blocks 21-24. The digital sum calculated in the first counters 4 (for the group 32 the digital sums is +2) is added in the second counter 14 with the previous value and the result of the addition is recorded in the memory block 11, etc. The prohibition block 12 eliminates the occurrence of prohibited digital sum values at the outputs of memory block 11 when the transmission system is turned on by setting memory block 11 to one of the allowed digital sum values. Thus, a five-level balanced signal is generated at the output of the first adder 18 the spectrum of which there is no constant component, and the power of the low-frequency components is insignificant. Therefore, the four-level signal at the output of the high-pass filter 16 is not distorted, and the interference power from the digital signal in the service connection canape at the output of the second adder 19 is negligible. The sum signal from the output of the second adder 19 is fed to the input of the frequency nodulator 15 and further to the radio path. It should be noted that the change in the values of phaea

frequency-manipulated signal

p 37

on, and, 11, - occurs on the time interval T, t T, which allows to expand the maximum opening of the chart at the outputs of the correlation receiver 30 and thereby increase the noise immunity of receiving digital information by reducing the effect of clock jitter phases on the inputs decision blocks 32 and 33.

At the receiving side, the signal from the output of the intermediate-frequency amplifier 29 is supplied to the controlled phase shifter 41 of the correlation receiver 30, which creates an initial phase shift between the signals fed to the multipliers 39 and 40. After multiplying and integrating in the low-pass filters 46 and 47, their outputs are formed binary signals. The outputs of the low-pass filters 46 and 47 are connected to the outputs of the selection unit 50, which isolates the voltage of the quadrature components in the first or third quadrants of the signal of the four-position frequency shift keying with a minimum shift.

The choice of the first or third quadrants is determined by the fact that in these quadrants the signs of the quadrature components are the same, which makes it possible to unambiguously determine the magnitude and sign of the error signal. The outputs of the selection unit 50 are connected to the inputs of the integrators 44 and 45, which form voltages applied to the error signal generator 42 and proportional to the average voltages of the quadrature components in the frequency-manipulated signal in the first or third quadrants.

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The error signal from the output of the imaging unit 42 is fed to the input of the controlled phase shifter 41, which compensates for the phase shift arising between the voltages supplied to the multipliers 39 and 40. And thus eliminates the reduction in the reception noise immunity due to the instability of the carrier frequency. The control signals arrive at the multipliers 39 and 40 through the delay element 43 and phase shifters 48 and 49. From the filter outputs 46 and 47 of the lower frequencies, the signals arrive at the first inputs of the decisive blocks 32 and 33, the second inputs of which are clocked

five

0

five

0

five

0

five

0

five

This signal is derived from the signals from the outputs of the filters 46 and 47 in the block 37 of restoring the boundaries of the linear premises. Binary sequences from the outputs of the first and second

decision blocks 32 and 33 are converted in decoder 35 into four binary sequences corresponding to the characters 0, 1, 2 and 3 of the 4th base, which arrive at resp. the respective inputs of the inverter 31 of the code base and the control block 37. From the output of block 37, signatures, - pass blocks 36 and 28, go to the other inputs of inverter 31. At its output, two digital streams are obtained, resulting from the inverse conversion of quaternary symbols into binary ones in accordance with the table. These two digital streams, passed through shaper 27, go to receiver 26. The normal operation of inverter 31 is provided by two pulse sequences, which follow with the frequency of information packets and the code group boundaries. The first of these sequences is created in block 28 of restoring the boundaries of information packages, and the second in block 36 of restoring the boundaries of code groups. Moreover, the overhead signals from the output of the amplifier 29 are fed to the overhead signal receiver 25.

Coding code violations in code S20 are understood as exceeding the limit values of the digital sum (s) that occur when there are erroneous characters in the received signal. At the same time, all single errors in the received signal lead to the increase of the limit values of the digital sum. The control unit 37 serves to detect violations of the digital sum limits, and the error is recorded in the recorder 38 by counting the errors in the counter 51 and indicating the readings in the display unit 52.

The technical and economic efficiency of the invention is associated with an increase in noise immunity, reception of digital information and, consequently, either with a decrease in the power of the transmitting station, or with an increase in the distance between the transmitting and receiving sides. The introduction on the transmitting side of the pulse former and the four coincidence blocks provides for the phase change of the frequency-manipulated signal with a minimum shift of 0,

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- II. - on the time interval T,

shorter duration of the clock interval of the transmitted digital signal, and thereby increases the area of maximum opening of the diagram's eyes at the inputs of the resolvers, virtually eliminating the influence of the phase jitter of the clock pulses on the noise immunity and making it easier to allocate the clock signal. .

Claims (1)

The invention The system of transmission of discrete information on author. St. No. 1262741, characterized in that, in order to improve noise immunity by reducing the effect of clock jitter, pulse generator and matching blocks are inputted on the transmitting side, each output of the gating unit is connected to the input of the first adder via the corresponding matching unit, the first output the linear parcel clock generator is connected to the pulse driver input, the KOtoporo output is connected to the second inputs of the matching blocks. 0} 1 / g. Compiled by O.Andrushko Editor G.Gerber Tehred M.Hodanich Proofreader M.Sharoshi Order 5448/56 Circulation 626 VNIIPI of the State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR It3035, Moscow, Zh-35, 4/5 Raushsk nab. Production and Publishing Combine Patent, Uzhgorod, st. Gagarin, 101 Subscription