SU928665A1 - Element-wise phasing device - Google Patents

Description

(54) DEVICE OF ELEMENTARY PHASING

The invention relates to the transmission of discrete messages and can be used to provide clock synchronization of the receiving part of the equipment. An elementary phasing device is known, which contains two reversible counters, two AND elements, a signal edge generator whose output is connected to the integrator information input, and a control unit connected in series and a controlled divider, the second output of the master oscillator is connected to the second input, and the first control output The splittable divider is connected to the first clock input of the phase discriminator and the input of the divider, the output of which is connected to the control input of the decoder, to the inputs of which is connected The integrator outputs are provided, and the decoder outputs are connected to the control inputs of the controllable divider, the second output of which is connected to the clock input of the control unit l. However, the device has a low noise immunity. . The purpose of the invention is to improve the premise resistance. The goal is achieved by the fact that the device is an elemental phasing, containing a reversible counter, two AND elements, a signal edge generator whose output is connected to the integrator's information input, and a serially connected control unit and a controlled divider, to the second input of which is connected the output of the master oscillator, and the first output of the controlled divider is connected to the first clock input of the phase discriminator and the input of the divider, the output of which is connected to the control input of the decoder, ko, to the inputs to The integrator's outputs are connected, and the deshi outputs (} (the eaters are connected to the control inputs of the controlled divider, the second output of which is connected to the clock input of the control unit, the signal converter, recording unit, reading unit, registration protection unit and averaging unit, outputs are entered which are connected to the summing and subtracting inputs of the control unit, and the first and second summing and subtracting inputs of the averaging block are connected respectively to the outputs of the fa-; a discriminator and a protection / registration unit, the third output of the controlled divider is connected to the clock input of the registration unit and the second clock input of the phase discriminator, while the second output of the signal edge generator, the first and the third are connected to the information input of the phase discriminator the outputs of which are connected respectively to the first and second inputs of the registration protection unit., and the output of the master oscillator is connected to the first inputs of the first and second elements I, with e th first output signal transducer connected to pervom.u. the input of the front of the signals, the first information input of the registration unit and the second input of the first element I, and the second output of the signal converter is connected to the second input of the forms, the front edge of the signals, the second input of the second element I and the second information input of the registration unit whose outputs are connected to the summing and to the subtractive inputs of the first reversible counter, the outputs of which are connected to the corresponding inputs of the subtractive unit, while the outputs of the first and second elements AND are connected respectively the summing and subtracting inputs of the second reversible counter, the outputs of which are connected to other relevant inputs of the subtractive unit, the outputs of which are connected to the control inputs of the signal converter, and the corresponding inputs of the first and second reversing counters, as well as to the control input of the reading section integrator output, to the reset input. Which is connected to the output of the divider. The drawing shows a block diagram of the device. The elemental phasing unit contains the registration unit 1, the first 9 54 reversible counter 2, the second reversing counter 3, the And t and 5 elements, the master oscillator 6, the divider 7, the decoder 8, the integrator 9, the subtracting block 10, the signal converter 11, the front 12 signals, phase discriminator 13, control unit, averaging unit 15, registration protection unit 16, controllable divider 17. The device operates as follows. The master oscillator 6 generates high frequency pulses, as a result of which the first and third outputs of the controlled divider 17 are formed at a frequency close to the transmission speed (wiring speed), two pulse sequences that are shifted relative to each other by half the follow-up period. At the same time, the output of the signal converter 11 generates the direct and inverse sequences of received message elements, and the leading and trailing edges of the received message elements from the second output form. the signal 12 front of the signal arrives at the information input of the phase discriminator 13. The phase discriminator 13 compares the phases of received message elements with the 4) clock pulse and, if they do not match, generates add or subtract corrective pulses that go to the first summing or subtracting input of the averaging unit 15, which protects the unit by element formation against false frequency tuning in case of random distortions in the communication channel of the received elements of the message. . The averaging correction signals are fed to the summing or subtracting inputs of control unit 1, which results in adjusting the phase and frequency of the clock pulses at the output of the controlled divider 17. The tuning step (sampling step) of the clock frequency is set by turning on the control unit 14 between the corresponding controlled bits divider 17, the switching point of control unit 1 being determined by the code of the number at the output of the decoder 8, i.e. the number of leading edges (the average frequency of alternating single and zero elements of the received message or their groups) received by the integrator 9 13a is the interval between two waste pulses at the output of divider 7, the conversion factor of which determines the moments of information input into the decoder 8. In addition, direct and inverse to the sequence of received elements, the messages from the outputs of the converter 11 of the signals arrive at the inputs of the registration unit 1 and the second inputs of the elements I and 5 to the first inputs of which the pulses come Frequency from the output of master oscillator 6. At the first and second outputs of block 1. of registration, pulses are formed corresponding to the arrival of a single or zero element of the received message, which arrive respectively at the summing and subtracting inputs of the first reversible counter 2, resulting in the first reversible counter 2, a certain number is written equal to the difference of the unit and zero elements of the received message for the time interval between the arrivals of the pulses at its fault input. Similarly, the second reversible counter 3 records the number that characterizes the difference between the single and zero elements of the received message and the difference of the durations of individual single and zero elements (the magnitude of the prevalence of current and current elements of the received message) for the same period of time. Information input into subtraction unit 10, as well as resetting of reversible counters 2 and 3, is performed by a signal from the output of the corresponding integrator 9, i.e. the time interval over which the readings of the reversing counters 2 and 3 are recorded varies depending on the frequency of alternation of single and zero elements in the received message. The subtractive unit 10 provides a comparison of the numbers (taking into account the specific weight of their bits) recorded in the reversible counters 2 and 3, forms at the output a code of a number that characterizes the prevalence of the received message elements. The signals from the output of the subtracting unit 10 are fed to the control inputs of the converter P signals, changing the threshold of its threshold element, resulting in a change in the prevalence of single and zero 5 elements at the outputs of the converter 11 signals. During the initial switching on of the equipment or after long interruptions in the operation of the communication channel, in the presence of prevalence, a gating pulse may be erroneously set, in which the registration unit 1 erroneously registers the received message elements. The phase adjustment of the clock pulses by means of the phase discriminator 13 with large predominance is difficult. Therefore, the functions of coarse output of the gating impulse to the correct position in this case are carried out by the registration protection unit 16, which checks the correctness of the alternation of the leading edge of the gating pulse and the trailing edge of the received message element. At the outputs of the registration protection block 16. In the event of false synchronization, depending on the type of dominance, add or subtract pulses are generated, which, through the averaging block 15 and the control block 14, act on the controlled divider 17, changing the phase of its output pulses. Thus, the unit-by-phase phasing unit provides increased noise immunity and reliability of information reception by the message transmission system as a whole, since the elements of the received message are subject to registration, the duration of which is corrected. Claims An elemental phasing apparatus comprising two reversible counters, two. element I, the front end of the signals, the output of which is connected to the information input of the integrator, as well as the control unit connected in series and the controlled divider, to the second input of which the output of the master oscillator is connected, and the first output of the controlled divider is connected to the first clock input of the phase discriminator and the input of the divider, the output of which is connected to the control input of the decoder, to the inputs of which is connected to the outputs of the integrator, - and the outputs of the decoder are connected to the control inputs by the control th divider, the second output of which is connected to the clock input block

control, characterized in that, in order to improve noise immunity, a signal converter, a recording unit, a subtracting unit, a registration protection unit1, and an averaging unit, whose outputs are connected to the summing and subtracting inputs of the control unit, and the first and second summing and subtractive inputs of the averaging unit

The outputs of the phase discriminator and the registration protection unit, respectively, have a third output of the controlled divider connected to the clock input of the registration unit and the second clock input of the phase IS discriminator, while the second output is connected to the information input of the phase discriminator. the front of the signals, the first and third outputs of which are connected respectively to the first and second inputs of the registration protection unit, and the output of the master oscillator is connected to the first inputs of the first and second elements 25, and the first output of the signal converter is connected to the first input pulse generator, the first information input of the registration unit and the second input of the first

element I, and the second output of the signal converter is connected to the second input of the front of signals, the second input of the second element I.and the second information input of the registration unit, the outputs of which are connected to the summing and subtracting inputs of the first reversible counter, the outputs of which are connected

block, while the outputs of the first and second elements And are connected respectively to the summing and subtracting inputs of the second reversible counter, the outputs of which are connected to other relevant inputs of the subtractive block, the outputs of which are connected to the control inputs of the signal converter, and to the reset inputs of the first and second reversible counters and the corresponding integrator output is connected to the control input of the subtracting unit, to the dump input of which the output of the divider is connected.

Sources of information taken by the attention in the examination

1. USSR author's certificate in application number 2920 89 / 18-09, cl. H 0 L 7/02, 1980 (prototype). the corresponding inputs of the subtractor

Claims (1)

Claim A phased phasing device containing two reversible counters, two. And element, a signal fritter, the output of which is connected to the information input of the integrator, as well as a series-connected control unit and a controlled divider, to the second input of which the output of the master oscillator is connected, and the first output of the controlled divider is connected to the first clock; the input of the phase discriminator and the input of the divider, the output of which is connected to the control input of the decoder, to the inputs of which the outputs of the integrator are connected, and the outputs of the decoder are connected to the control inputs of the controlled divider, the second output of which is connected to the clock input of the unit * Ί 928665 θ of the control, which differs in the AND element, and the second output is transformed so that, in order to increase noise immunity, a signal converter, a registration unit, a subtracting unit, a registration protection unit !, $ and an averaging unit whose outputs are connected to the summing and subtracting inputs of the unit are introduced control, and to the first and second summing and subtracting inputs of the averaging block, the outputs of the phase discriminator and the registration protection block, respectively, are connected to the clock input of which, as well as to the clock input of the registration block and and a second clock input of the phase discriminator is connected 1S Vågå managed third output divider, the data input to the phase discriminator is connected to the second output. of a signal fritter, the first and third outputs of which are connected respectively to the first and second inputs of the registration protection unit, and the output of the master oscillator is connected to the first inputs of the first and second electronic signals AND, while the first output of the signal converter is connected to <the first the input of the pulse shaper, the first information input of the registration unit and the second input of the first signal generator is connected to the second input of the signal fritter, the second input of the second element And the second information mu input of the registration unit, the outputs of which are connected to the summing and subtracting inputs of the first reversible counter, the outputs of which are connected to the corresponding inputs of the subtracting block, while the outputs of the first and second elements And are connected respectively to the summing and subtracting inputs of the second reversible counter, the outputs of which are connected to other the corresponding inputs of the subtracting unit, the outputs of which are connected to the control inputs of the signal converter, and to the reset inputs of the first and second reversible counters, as well as to the control input of the subtracting unit, the corresponding output of the integrators is connected, to the discharge input of which the output of the divider is connected.