SU688082A1 - Discrete information transmission system - Google Patents

Description

The invention relates to telecommunications. A known system for transmitting discrete information contains on the transmitting side a source of bottom information, a pulse shaper and a synchronization unit, and on the receiving side - a linear amplifier, an optimal signal processing unit, a rectifier and a deciding unit, and the output of the rectifier through the threshold voltage shaping unit and the linear parcel boundary restoring unit are connected to other inputs of the decision unit; the additional outputs of the threshold voltage shaping unit are connected to a control input of a linear Wuxi divisor and to another input of the Sun Formation grlnits linear parcels and - serially connected binary signal generator and the consumer discrete information 1. However, the known system has a relatively low bandwidth. The aim of the invention is to increase throughput. For this purpose, a discrete information transmission system containing a discrete information source, a pulse signal generator and a synchronization unit on the transmitting side, and a serially connected linear amplifier, an optimal signal processing unit, a rectifier and a solver unit, and the rectifier output through the block forming the voltage threshold and the unit for restoring the boundaries of the linear premises are connected to other rods of the decision block; additional outputs of the voltage threshold shaping unit are connected to the control input of the linear amplifier and to the other input of the linear parcel boundary recovery unit, as well as the serially connected binary signal generator and the consumer of discrete information, an encoder is entered on the transmitting side, and a decoder and error recorder on the receiving side, and a discrete source information through the encoder is connected to the input of the pulse shaper signal, the output of the synchronization unit is connected to another input

the encoder, the outputs of the decision block are connected to the inputs of the error recorder and, through a decoder, the outputs of the rectifier and the block of restoring the boundaries of the linear packages are connected to the other inputs of the decoder, the other output of which is connected to another input of the error register, and the decision unit is made the form of a block of triple decisions. At the same time, the encoder is designed as a signal base converter, the clock inputs of which are connected to the code generator clock outputs and the sync signal generator of the linear parcels, whose input is connected to another output of the code clock generator, the input of which is connected to the output of the synchronization unit, which forms a pulse signal made in the form of a generator of a three-point amplitude-difference monopulse signal and contains an output adder, the inputs of which are connected to you The encoder decoder's base converter transforms are made in the form of a signal base inverter, the synchronization inputs of which are connected to the outputs of the code group boundary recovery block and information packages edge recovery block, the input of which is connected to the output of the code group boundary recovery block whose inputs are connected to the output of the rectifier and the output of the unit for restoring the boundaries of linear premises the error recorder is designed as a series-connected element OR, the first the counter and the display unit, another input of which is connected to the second input of the first counter via the second counter, the inputs of the OR element and the second input of the first counter connected to the outputs of the ternary decision block, and the other input of the second counter connected to the output of the boundary restoration block code groups.

Figure 1 shows the structural electrical circuit of the proposed system; in fig. 2 shows timing diagrams for explaining the process of forming a three-position amplitude difference monopulse signal; FIG. 3 shows timing charts explaining the process of receiving and restoring the transmission rate.

The discrete information transfer system contains on the transmitting side a source of 1 discrete information, a synchronization unit 2, an encoder 3 and a driver, 4 pulses, and the encoder 3 consists of converting the signal base bodies 5, the code group generator 6, and the sensor 7 generator. parcels; shaper 4 you

It is filled in the form of a three-position amplitude-difference monopulse signal generator and consists of an output adder 8 and two counting triggers 9, 10.

On the receiving side, the system contains a linear amplifier 11, a block 12 for optimal signal processing, a rectifier 13, a decisive block 14 made in the form of a decision block, a block 15 for shaping the threshold voltage, a block 16 for restoring linear bounds, a decoder 17, a recorder errors 18, a binary signal generator 19 and a discrete information consumer 20, the decoder 17 consisting of a signal base inverter 21, a code group edge recovery unit 22, and osylok error logger 18 includes OR gate 24, two counters 25, 26 and display unit 27,

The system works as follows.

The dioic digital signal (Fig. 2a) of source 1 is fed to converter 5 of encoder 3. From a periodic sequence of pulses (Fig. 26 of synchronization unit 2 in generators b and 7, two periodic sequences of pulses are generated following the frequency of code groups (Fig. 2b) and with the frequency of linear (secondary workers) parcels (FIG. 2d).

According to the following tab; the binary conversion system of the binary system is ternary (code table)

Binary ternary group.

01 02 10 11 12 20 21 22

and with the help of periodic sequences of pulses (Fig. 2c, d), two pulse sequences are formed at the output of converter 5, which characterize the appearance of the second (Fig. 2d) and third (Fig. 2e) ternary symbol.

When a second ternary symbol is generated in the encoder 3, the state of the first counting trigger 9 changes, and the third ternary symbol's signal controls the state of the second counting trigger 10.

The formation of a linear signal with different changes in the voltages of the switching of the first and second counting triggers 9, 10 (fig.2h, e) is achieved by summing the output voltages of the trigger 9, 10 in the adder 8 with the corresponding weighting factors (fig.2i).

. At the receiving side, the received signal (Fig. 3A) is amplified by a linear amplifier 11 and processed in block 12 in the interval of two adjacent work parcels.

After optimal processing in block 12 and non-linear conversion in rectifier 13, the received signal goes to decision block 14, as well as to threshold voltage generating unit 15 and to the linear parcel boundary restoring block 16.

One of the voltages created in block 15 controls the gain of the linear amplifier li.

Decisions on the reception of tricyc characters are formed in the decision block 14 by the value of the processed signal (Fig.Zb) relative to the threshold voltages of the 1b block (dotted lines in Fig.Zb) at the moments of the appearance of short pulses at the boundaries of secondary working (linear) parcels created block 15 (fig.Zv).

The decisions to receive the first (fig. 3 of the second (fig. 3) and third (fig. 3 ternary symbols, taken in decision block 14) are fed to the invertor 21 of the base signal of the decoder 17. Its normal operation is provided by a periodic sequence of pulses following boundaries of code groups (fig.Zh) and on the borders of information packages (fig.Zz).

The first of the sequences is created in block 22 of restoring the boundaries of code groups, and the second in block 23 of restoring the boundaries of information packets.

In block 23, the indicated boundaries are formed by multiplying by three frequencies the L repetition pulses at the boundaries of the Code Groups.

At the output of the decoder 17, two digital streams are formed, obtained as a result of the inverse transformation of ternary solutions into binary ones in accordance with the above code table. At the same time, one of the streams characterizes by drinking the first, binary symbol (fig.Zi), and the other of the second binary symbol (fig.Зк). Using these streams, the binary signal generator 19 generates a discrete information signal to the consumer 20 (FIG. 3L), which coincides in shape with the original (FIG. 2a).

The control over the quality of information passing through the regeneration section is carried out in the recorder of Error 18 by detecting three ;; more decisions about accepting the first trinity from a symbol in the absence of decisions about accepting the second and third symbols. Therefore, the decisions taken in the decision block 14 on the second and third symbols through the OR element 24 of the collection. put the counter 25, and his counting

the input is controlled by decision pulses. on the first threefold character. The display unit 27 averages the readings of the counter 25 and registers the probability of the occurrence of errors

S When receiving signals at the terminal station, errors accumulated in the communication line are detected by a counter 26 on the appearance of a forbidden code group consisting of the first two

0 ternary OS symbols coming from decision block 14, counter 2b is reset by pulses from block 22. The proposed system allows to increase throughput,

5 since, as the linear velocity decreases by one and a half times, it does not require the addition of additional information to the signal in order to form a sync signal of the frequency of linear premises and to detect errors.

0

Claims (1)

Invention Formula ; 1, the transmission system is discrete information contained on the icTOpoHe transmitting source of discrete information, a pulse signal generator and a synchronization unit, and on the receiving side - serially connected linear amplifier, an optimal signal processing unit, a receiver and a decision unit, with the rectifier output through the threshold voltage shaping unit and block the linear parcel boundary restoration is connected to other inputs of the decision unit, the additional outputs of the threshold voltage shaping unit are connected to the control input of the linear amplifier and to the other input of the linear package border recovery unit, as well as the serially connected binary driver signal and consumer discrete 55 information different to that. In order to increase the bandwidth, a coder and an error coder are entered at the transmitter side, and a decoder and error recorder are input at the receiving side, the encoder source is connected to the input of a pulse signal generator through the encoder, the output of the synchronization unit is connected to another encoder input, the block is connected to the inputs of the error recorder and, through a decoder, to the inputs of the binary package generator, the outputs of the rectifier and the block recovery unit of the linear packages are connected to other decoder inputs, another output to torogo connected to another input of the fault memory, and deciding unit is configured as a block received five ternary solutions. 2, Pop-up system 1, characterized in that the encoder is made in the form of a signal base converter, the synchronization inputs of which are connected to the outputs of the code group clock generator and the linear signal clock generator, the input of which is connected to another output of the code group clock generator whose input is connected with the output of the synchronization unit. 3. The system of PP. 1 and 2, which differs in that the pulse signal generator is made in the form of a generator of a three-position amplitude-difference monopulse signal and contains an output adder, the inputs of which are connected to the outputs of the converter base of the encoder signal. 4. The system of PP. - 3, that is, the decoder is designed as an inverse converter of the signal base, the synchronization inputs of which are connected to the outputs of the code group boundary recovery block and information package edge recovery block, the input of which is connected to the code group boundary recovery block, inputs which are connected to the output of the rectifier and the output of the block of restoring the boundaries of linear parcels, 5, System on PP. 1-.4, characterized in that the error recorder is designed as a series-connected element OR, a first counter and a display unit, another input of which is connected to the second input of the first counter via a second counter, the inputs of the OR element and the second input of the first counter connected to the outputs of the unit make triple decisions, and the other input of the second counter is connected to the output of the unit for restoring the boundaries of code groups. Sources of information taken into account in the examination 1. USSR author's certificate 524469, cl. H 04 L 27/22, 1973 (prototype). about e b .zh