SU540402A1 - Frequency demodulator - Google Patents

Description

one

The device relates to radio engineering and can be used in receivers of discrete frequency malapulirovannyh signals.

A frequency demodulator is known that contains a reset circuit, to the input of which clock pulses are fed, and a series-connected limiter, a differentiating circuit, and a reference trigger 1.

The purpose of the invention is to improve noise immunity.

For this purpose, a comparison circuit and l circuits, each of which consists of a series-connected delay element, trigger, modulator, are introduced into the frequency detector containing a reset circuit, to the input of which clock pulses are fed and series-connected limiter, differentiating circuit and reference trigger. two, coincidence and counter circuits (where is the number of channels), the output of the reset circuit is connected to the second inputs of the counters, the outputs of which are connected to the comparison circuit, and the output of the differentiating circuit is connected to the control to the inputs of the delay elements, the OUTPUT of the reference trigger is connected to the second inputs of modulo two adders, and the pa second inputs of the matching circuits are clocked.

The drawing shows a frequency modulator circuit for the number of channels.

The frequency demodulator contains a reset circuit 1, to the input of which clock pulses are applied, connected in series by limiter 2, differentiating circuit 3 and

a reference trigger 4, as well as a comparison circuit 5 and a circuit 6-1 and 6-2, each of which consists of a series-connected delay element 7, a trigger 8, an adder 9 modulo two, a coincidence circuit 10, and a counter 11.

The frequency demodulator works as follows.

In limiter 2 there is an inertial two-way limiting of the signal from the output of the linear part of the receiver. The pulses corresponding to the fronts of the limited signals through the differentiating circuit 3 arrive at the counting input of the reference trigger 4 and on the identical circuits 6-1 and 6-2, the number of which in general corresponds to the number of frequencies distinguished during demodulation.

The trigger 8 in each of the circuits 6-1 n 6-2 recalculates the pulses delayed by delay element 7, and modulo two adder 9 calculates the inequality function between the input signal sections shifted by the time determined by delay element 7. Output adder 9 to

Claims (1)

module two controls the clock through impulses to counter 11 via a clock. The readings of counters AND of circuits 6-1 and 6-2 are compared to the minimum at the end of the averaging period by comparison circuit 5, the output of which is the output of the frequency demodulator. The initial installation of the counters 11 is made after comparing their readings with the CpaBHeHKH 5 circuit. Formula of the Invention A frequency demodulator containing a reset circuit, the input of which is clocked, and a series-connected limiter, a differentiating circuit and a reference trigger, characterized in that , introducing a comparison circuit and n circuits, each of which consists of successively connected delay elements, a trigger, an accumulator but two modules, a coincidence circuit, and a counter (where and is the number of channels the output of the reset circuit is connected to the second inputs of the counters, the outputs of which are connected to the comparison circuit, and the output of the differentiating circuit is connected to the control inputs of the delay elements, and the output of the reference trigger is connected to the second inputs of the modulo adders and the second inputs matching circuits are clocked. The source of information taken into account in the examination: 1. Shl Pobersky, V. I. Basics of the Technique for the Transmission of Discrete Messages, M., “Link, 1973, p. 213 (prototype).