SU1405020A1 - Electronic watch with correction of indicatings by standard time signals - Google Patents

Abstract

The invention relates to devices providing automatic selection of reference time signals and correction of scales of digital time devices. The purpose of the invention is to reduce the recovery time of the formed scale and reduce the permissible accuracy of the initial installation. The device contains a receiver 1 signals, a driver 2 pulses, a circuit AND 6, a decoder 7, a trigger 4, an indicator 12, a crystal oscillator 13, a divider 14 frequency, counters time 15, seconds 16, minutes 17 and hours 18. The introduction of reference counters 3 and B, the circuit OR 5, the circuits AND 9 and 11, the bus Reset 19, the bus Start 20 and the trigger 10 and the formation of new connections between the elements of the device allows correct correction of the formed scale if it is 20 s behind the state standard or 20 s ahead of it g Correction of the formed scale takes place during the passage of 3 min pulses. 1 il. pp SP N0

Description

: The invention relates to a device - | gtroenii, in particular to devices | to ensure the automatic enhancement of reference time signals and: the correction of the scales of digital time devices.

The purpose of the invention is to reduce time. restoring the formed scale and reducing the permissible accuracy of the initial installation.

The drawing shows a block diagram of the clock.

The clock consists of a receiver 1 signals, a driver 2 pulses, a reference counter 3, a trigger 4, an OR circuit 5, an AND 6 circuit, a decoder 7, a reference counter 8, an AND 9 circuit, a U trigger, an 11 circuit, an indicator 12, a crystal oscillator 13, the frequency divider 14, the time counter 15, which contains the seconds 16 counters, 17 minutes and 18 hours, Reset 19 tires and Start 20 tires.

In the device, the output of the crystal oscillator 13 is connected to the first input of the frequency divider 14, the first output of which is connected to the counting input of the time counter 15. The output of the receiver 1 of the signals is connected to the input of the pulse former 2, the inverse output of which is connected to the installation input to O of the reference counter 3 and to the first input of the AND 9 circuit. The second output of the frequency divider 14 is connected to the counting inputs of the reference counters 3 and B, the first of the installation inputs in About reference counter 8 is connected to the output of the AND 9 circuit, and the second to the output of the OR 5 circuit and to the installation input of 1 flip-flop 4, the direct output of which is connected to the second input of the AND 9 circuit. Parallel outputs of the bits of the reference counter 8 are connected with entrances de 7. The first output of the reference counter 3 is connected to the input of the installation in O of the trigger 4 and with the inverse input of the circuit AND 6, the second output of the reference counter 3 is connected to the first input of the OR circuit 5, the second input of which is connected to the input of the installation in About the trigger 10 and with bus Reset 19, the third input of the OR circuit 5 is connected to the first output of the decoder 7, to the first input of the AND 11 circuit and to the second input of the installation in O of the trigger 10, a fourth input of the OR circuit 5 is connected to the output of the And 6 circuit, direct input which

five

0

five

0

five

0

five

0

five

It is connected with the second output of the decoder 7. The direct output of the trigger 10 is connected to the indicator 12 and to the second input of the circuit 11, the output of the correction signal of which is connected to the inputs of the O frequency divider 14 and the counter 16 seconds. The installation input in the On trigger 10 is connected to the Start 2Q bus

The device works as follows.

Before starting work on the bus, Reset 19 is supplied with a short-time signal, which sets the RS flip-flop 10 to O and sets the reference counter 8 to the O and 1 sets the RS-flip-flop 4. Signal receiver 1 (radio receiver) is tuned to the signal transmission frequency the exact time, low-frequency oscillations are formed at its tonal output when high-frequency radio signals are present at the input corresponding to second, minute, and other (including interference) signals. The pulse former 2 in the simplest case is a low frequency detector that forms the envelope of low frequency signals and converts the voltage levels into logic levels necessary for the operation of the logical nodes of the device, while in the presence of a receiver at the input 1 of the signals at the inverse output of the pulse former 2 the logical level is O and, on the contrary, in the absence, the logical level is 1, which keeps the reference counter 3 at zero and, through the AND 9 scheme, the reference counter 8, since the RS-t output igger 4 to the second input of the circuit And 9 is given a permitting signal 1, If there are 2 pulses of logic level O at the output of the imager (if there is a radio signal at the input of receiver 1 of the signals), the reference counters 3 and 8, summing impulses with stable output periods divider 14 frequencies coming to their counting inputs. If the radio signal corresponds to a minute pulse (500 ms duration), then the reference counter 3, counting the reference time T, (always constant and equal to the permissible accuracy of about 500 ms), will generate a pulse of the reference duration T, which is equal to the sum of the absolute allowable

errors in the plus and minus on the hardware error of the data, for example, if the absolute hardware error error is ± ms, then T g 2 ms With this pulse, RS-flip-flop 4 is set to O, which is output from the RS-flip-flop 4 to the second The input is schematically, if the signal from the second output of the decoder 7 is invested in time into a signal with a duration T from the first output of the reference counter 3, then phasing occurs with permissible accuracy and the reference counter 8 continues the summation of pulses entering its account a first input

we And 9 and further prohibits resetting the Q divider frequency 14, Otherwise, the second reference counter 8 from the output of the driver 2 pulses. If the radio signal at the input of the receiving device 1 is shorter than the duration T, then the pulse at the first output of the reference counter 3 does not form and during the pause between the radio signals, the reference counter 8 is held in the zero state, because the RS flip-flop 4 does not switch to 0. If the radio signal is at the input receiving device 1 is long if there is no signal from the output of the decoder 7 at the direct input of circuit 6, the signal of the inverting input of circuit 6 is not acceptable - the accuracy is 12, the phasing is not reached and the output of circuit 6 appears The OR 5 circuit sets the RS trigger 4 and the reference counter 8 to the initial states, and the whole process of extracting the minute pulses and checking the correctness of the phasing is automatically repeated. With proper phasing after 20

In addition, if there is a pulse from the output of the decoder 7 at the forward input of circuit 6, the signal does not reach the inverting input of circuit AND 6 - the tolerance is acceptable, the phasing is not reached and a pulse appears through the circuit output AND 6 setting the RS-flip-flop 4 and the reference counter 8 to the initial states, and the whole process of extracting the minute pulses and checking the correctness of the phasing automatically repeats. When correctly phased, after the reference counter 8 is counted 500 not, then when it reaches the reference counter 3 time audio Ts (more 500 ms with a permissible error)

At the second output of the first reference 25, time 2 min, at the first output of the descriptor 3, the level appears, the encoder 7 appears shortly

drawing a scheme OR 5 RS-trigger-pulse, which through the scheme OR 5 usger 4 and the reference counter 8 in the initial set RS-trigger 4 and the reference

condition. Thus, the reference counter 8 to its original state and in

counter 3 performs the function of a selector d time arrives at the first input

radio signals by duration. If the circuit And 11, In this case, if earlier

Minute pass was recorded. Start 20 received a short signal pulse with a duration of 500 ms, then from the output of the RS flip-flop 4, the logic level O disables the reset of the reference

then, the RS flip-flop 10 is set to one and the enabling input is present at the second input of the AND 11 circuit.

the counter 8 to O and the counter 8 are summed - the level, therefore the signal from the first one is outputted by the pulses arriving at its counter of the decoder 7 passes through the inlet when the second AND 11 circuit reaches the zero divider 14 frequency and the counter is 16 seconds and simultaneously sets The RS-flip-flop 10 returns to the initial zero state. The indicator 12 indicates the signal passing through the bus Start 20, i.e.

by a common counter 8 values Td 1 min + T, + DT, where T is the reference time of the first reference counter 8; l T - absolute hardware error minus error.

At the second output of the decoder 7, a short pulse is formed with a power much less than the permissible error T, which is fed to the direct input of the AND 6 circuit. If the phasing was correct, then

40

circuit 11 for resetting the divider 14 frequency and the counter for 16 seconds and simultaneously sets the RS-flip-flop 10 to the initial zero state. The indicator 12 indicates the signal flow on the bus Start 20, i.e.

is displayed when installed in

I

45

RS-flip-flop 10, therefore quenching the indicator means the passage of a correction impulse. If the seconds counters are 16, 17 minutes, and 18 hours are binary decimal counters with sequential carry (which

the moment at the input of the receiving device usually takes place), then the 1 is present during the time T, if the highest bit is a counter-minute signal (with a duration of 500 ms) and formed on the first

ka 16 seconds is zero, then the value of seconds is in the interval (0-39) dec. and resetting the counter to 16 seconds with a correction pulse does not entail switching the counter for 17 minutes; if the high-order counter of 16 seconds is one, then the value of seconds

the output of the reference counter 3 pulse of duration T, arriving at the inverting input of the circuit AND 6 blocks the passage of a pulse from the second output of the decoder 7 to the input of the circuit OR 5.

In addition, if there is a pulse from the output of the decoder 7 at the forward input of circuit 6, there is no signal at the inverting input of circuit AND 6 - the accuracy is acceptable, the phasing is not reached, and a pulse appears at the output of circuit 6 - sets the RS-flip-flop 4 and the reference counter 8 to the initial states, and the whole process of extracting the minute pulses and checking the correctness of the phasing is automatically repeated. With proper phasing after

go, as the counter 8 is counted, the RS flip-flop 10 is set to one and the enabling input is present at the second input of the AND 11 circuit.

level, so the signal from the first output of the decoder 7 passes through

level, so the signal from the first output of the decoder 7 passes through

circuit 11 for resetting the divider 14 frequency and the counter for 16 seconds and simultaneously sets the RS-flip-flop to the initial zero state 10. The indicator 12 indicates the signal flow through the bus Start 20, i.e.

is displayed when installed in

I

RS-flip-flop 10, so the quenching of the indicator means the passage of the correction pulse. If the seconds counters are 16, the minutes 17, and the hours 18 are binary-decimal counters with sequential transfer (what.

usually takes place), therefore, if the highest bit of counters is

usually takes place), therefore, if the highest bit of counters is

ka 16 seconds is zero, then the value of seconds is in the interval (0-39) dec. and resetting the counter to 16 seconds with a correction pulse does not entail switching the counter for 17 minutes; if the high-order counter of 16 seconds is one, then the value of seconds

are in the interval (40-59) dec, and resetting the counter to 16 seconds with a correction impulse causes the counter to switch 17 minutes to 1, since at the counting input of the counter 17 minutes the level drops. Consequently, in the proposed device, the correct correction of the formed scale occurs if it: lags behind the state standard by 20 s or is ahead of the state standard by 39 s. Correction of the formed scale occurs during the passage of three minute pulses, i.e. during at least two minutes and at most three minutes (since minute signals are transmitted around the clock and continuously).

Claims (1)

Invention Formula Electronic clock with correction of readings by reference time signals containing a receiver of signals, a pulse shaper, a trigger, an AND circuit, an indicator, a decoder and a series-connected crystal oscillator, a frequency divider and a time counter, the output of the signal receiver is connected to the pulse shaper input, the setup input About the seconds counter of the time counter is connected to the installation input About the frequency divider and to the output of the I circuit, the first input of which is connected to the output of the decoder and to the first trigger input, output of the connections with the indicator, characterized in that. five 0 five 0 five In order to reduce the recovery time of the formed scale: and reduce the permissible accuracy of the initial installation, two reference counters, the second and third AND circuit, the OR circuit, the second trigger, the Reset bus, and the Start bus, are added to the electronic clock, with the pulse driver output connected to the first input of the first the reference counter and to the first input of the second circuit I, the second input connected to the output of the second trigger, and the output to the first input of the second reference counter, the second input of which is connected to the second input of the first the reference meter and the second output of the frequency divider, the third input of the second reference meter is connected to the first input of the second trigger and to the output of the OR circuit. the outputs of the bits of the second reference counter are connected to the corresponding inputs of the decoder, the first output of the first reference counter is connected to the second input of the second trigger and the inverse input of the third circuit AND, and the second output to the first input of the OR circuit, the second input of which is connected to the second input of the first trigger and the reset bus, the third input is to the first output of the decoder, and the fourth input is to the output of the third I circuit, the direct input of which is connected to the second output of the decoder, while the third input of the first trigger is connected to the Start bus and the output is to the second input of the first circuit I.