SU1218484A1 - Device for synchronizing with respect to m-sequence - Google Patents

Abstract

The invention may be used in communication systems with noise-like signals. The time to synchronization is reduced while simultaneously increasing the confidence in establishing the presence of synchronism. The signal of the received M-sequence (ml) passes through filter 1 to a level 10 detector: and to block 2, itemwise reception. From this block, the MP characters are written to the shift register 3 (PC) directly, and to PC 4 through the first channel of the two-channel multiplexer 16. When PC 3 and 4 are fully populated, the signal is log. 1, the K-th bit of PC 4 sets the RS flip-flop 5 to state 1. As a result, based on PC 4, using the EXCLUSIVE OR .1 1 element and switching the two-channel multiplexer 16 to the second channel, a local M-pic generator is formed (L 00 41 QO

Description

ice stream. The segments of the received, mine and local MP, respectively, with PC 3 and PC 4 are compared in a digital comparator 15 .. If during the if cycles there is an undistorted reception of the MP, then the signal log. 1 from the direct output of counter 9 blocks it. This signal can be used as a sync signal. In case of violation of synchronization of the signal log. 1 with a digital comparator allows the counter 8 to count the pulses of the generator 7 clock pulses. ESG

The invention relates to radio communications and can be used in communication systems with noise-like signals.

The purpose of the invention is to reduce the time of entry into synchronism while at the same time increasing the reliability of establishing the presence of synchronism.

The drawing shows a structural electrical circuit of the synchronization device with the M-sequence.

The synchronization device with the M-sequence contains a filter 1, block 2 element-wise reception, the main K-bit register 3 shift, additional K-bit register 4 shift, RS-flip-flop 5 divider 6 frequency, generator 7 clock pulses, first 8 and second 9 counters, level 10 detector, an element EXCLUSIVE OR 11, is formed. The driver 12 sets the initial state, the first 13 and second 14 elements OR, the digital comparator 15, a two-channel multiplexer 16. The initial state set 12 impulses of the initial state contains a D-flip-flop 17, an integrator 18.

The synchronization device with the M-sequence works as follows.

In the initial state (in the absence of a signal at the device input and power on), at the output of the level 10 detector, a sync breakdown is formed more than specified, then the signal log. 1 from the counter 8 is fed to the shaper 12 of the pulses for setting the initial state. The impulse from the block through the IDI element 13 sets the PC 3.4 and the RS flip-flop 5 to the initial state. The frequency transducer 6 and the OR 14 element specify the duration of the MP segment on which the asynchrony is determined by zeroing the counter 8. 1 Cpf-ly 1 Il.

Cash corresponding to logic 1 This signal sets the initial 3 (ground) state of the primary 3 and the additional 4 K-bit shift registers and the RS flip-flop 5. To the inverse output of the RS flip-flop 5, the signal corresponding to the logical 1. It is fed to the R input of the Second counter 9, which, by the action of this signal, is set and held in the zero state. As a result, the first counter 8 at the R input through the second SHSh 14 element is set and held in the zero state by the inverse output of the second counter 9. The signal of the received M-sequence is filtered in filter 1 and fed to block 2 by element receive and 10 level detector As a level 10 detector, for example, an amplitude detector with an inverter at the output can be applied. In unit 2 of element-wise reception, as the M-sequence symbols arrive, they are evaluated and written to the main K-bit shift register 3. Unit-by-element reception 2 can be performed, for example, on a D-flip-flop, the information D-input of which is connected to the main input of unit 2 of a single-tier reception, the auxiliary input of which is connected to the clock C-D of the flip-flop, with exit block3

ka 2 elementwise reception. The signals from the outputs of RS-flip-flop 5 provide the inclusion of the first channel of the two-channel multiplexer 16. As multiplexer 16, an element can be used that implements the function F XVj (or YVa, where V and V and control signals. Through the first channel of the two-channel multiplexer 16 on the input of the additional K-bit register 4 of the shift is received from the output of the block 2 of element-by-element reception. Both the K-bit register 3 and 4 of the shift are simultaneously synchronized with elements of the M-sequence. yes add The K-bit shift register 4 of the shift signal of logic 1 is fed to the setup S-input of the RS-flip-flop 5 and sets it to the one state. A change of the RS-flip-flop 5 causes the switching of the mutest 16 channel and the removal of the holding on the R-input the signal from the second counter 9. The signals formed by the EXCLUSIVE OR 11 element from the input signals of the corresponding bits of the additional K-bit register 4 shift arrive at the input of the second channel of the multiplexer 16 to the input of the additional K-bit register 4 shift. Due to such a connection, a local M-sequence generator is formed on the additional K-bit shift register 4. This generator is obtained by the same connections of the EXTENDER OR P element, similar to the generator of the transmitting side M-sequence. Therefore, after the additional K-bit shift register 4 is filled with elements of the received M-sequence, switching its input from the output of the element-by-element reception unit 2 to the output of the EXCLUSIVE OR element causes the additional K-bit shift register 4 to autonomously synchronize with the received M -sequence. The segments of the received and local M-sequences formed at the outputs of the K-bits of the basic and additional K-bit registers of 3.4 shift are compared in a digital comparator 15. As a quality 18484

digital comparator 15 can be applied to the element that implements the th function

p. (, w., (A, ®B, 1- (A2®8.1- (A, 0B,

where A, Bt-K-bit comparable numbers;

(+) - modulo two summation.

With undistorted reception of the M-sequence, the output of the digital comparator 15 is a logical O signal. First counter 8

0

five

when this is the counting of clock pulses from the generator 7 clock pulses at its C-input. If the uncorrupted reception of the M-sequence continues for N cycles, then the signals at the outputs of the second counter 9 change: the logical output is set to logical 1, and the logical output on the inverse. O. Signal from forward and 1- N -The size of the second counter 9 is fed to its resolving, the account is the V-input and blocks the long-distance account. The same signal can be used in external circuits as a synchronization signal. : N elements of the M-sequence, which must be taken when coinciding with elements of the local M-sequence, can be determined from the formula

0

: .p (- (

- (| |

{K-lNlR

.

0

five

0

where P is the probability of receiving M subsequently. the agency;

P is the probability of a single error, kk for a communication channel; - probability of no error in the communication channel; N is the minimum number of elements of the sequence of the sequence that satisfies the law of formation of the M-sequence; K is the number of elements in the M-sequence; at K to (4-6) N J

ii.

eleven

il at (4-5) N.

UO

In the device, this number of elements is established by the volume of the second counter 9. As the first 8 and

The second 9 counters in the device can be used in the form of integrated circuits. After counting the N elements by the second account, the device 9 goes into the synchronization preservation tracking mode. If synchronism is maintained, then the digital comparator 15 outputs a logical JQ P signal, which prohibits the clock counting by the first counter 8. When the synchronization fails, the digital comparator 15 outputs a logical 1 signal, which J5 goes to the enabling account (Y- the input with the inversion of the first counter 8 and allows it to count the clock pulses received at the clock C input with inversion. The clock C input 20 with the inversion at the first counter 8 is used to separate the counting processes of the first 8 and second 9 counters, which eliminates failures in the formation of initial setup pulses by their signals. If a synchronization failure occurs on the number of elements more than specified for the specified M-sequence, then the ZO overflows the first counter B. Signal logical 1 from the output of the first counter 8 D-flip-flop 17 of the driver 12 of the pulses of the initial state setting is transferred to the single state at the S-input. The logical 1 signal from the direct output of the D-flip-flop 17 lasts until the logical 1 JQ signal is established at the output of the integrator 18 By selecting the time constant of this circuit and setting the pulse width of the initial setting sufficient to translate into the initial state and additional K-bit registers 3,4 shift: and RS-flip-flop 5 through the first element OR 13. The pulse of the initial setup in this case switches the device to the synchronization setting mode. The duration of the M-sequence, for which a number of elements not received in synchronism with the local sequence elements, is given by the frequency divider 6 due dividing clock frequencies in sequence as often as required and to periodic zeroing the first counter 8

35

45

50

, JQ J5 20 25 ZO Q

five

five

0

through the second element OR 14 impulses-- the divider itself is 6 frequencies. When only noise arrives at the device input, the level of which reaches the signal level, the logic 1 yo signals at the output of the digital comparator 15 are before the overflow of the second counter 9. As a result, the logic 1 signal applied to the D-flip-flop 17 The digital information D-Bxofltc inverse output of the second counter 9 with each digital comparator 15 signal due to the effect of this signal on the clock C input of the D flip-flop 17. The generated initial setup pulse returns the device to similar condition.

When the signal level at the input of the device is lower than that established by the working output of the detector 10 level, there is a logical J signal that keeps the device in the initial state. The magnitude of the operating signal level can be set by changing the characteristics of the detector 10 level.

Claims (3)

1. A synchronization device with an M-sequence containing at the input a series-connected filter and a block-wise reception unit whose output is connected to the information D-input of the main K-bit shift register, as well as an RS flip-flop, an additional K-bit register the shift and clock generator, the output of which is connected to the input of the frequency divider, which is so that, in order to reduce the time required for synchronization while simultaneously increasing the reliability, neither synchronism nor l: digital comparator, two-channel multiplexer, the first and second counters, the first and second elements OR, the level detector, the EXTENDANT OR element and the initial state setting pulse generator, to the first input of which and the V-input of the first counter allowing the counting, the digital output is connected the comparator, and the pulse generator setpoint setting of the initial socket is connected to the first input of the first OR element, to the second input of which a filter output is connected through a level detector, while the first output of the first counter It is connected to the second input of the pulse setting unit of the initial state, to the third input of which and the first input of the second element OR the inverse output of the second counter, the direct output of which is connected to the counting V input, is connected to the clock input C of the second counter, as well as to the clock C-inputs of the first counter, the main and additional K-razdnyh shift registers, to the additional input of the element-wise reception unit the output of the clock pulse generator is connected, and to the installation R-input of the first center tchika connected to the output of the second member ISCH to the second input of which is connected the output frequency selective divider and to the installation R-input of the second counter and the first control input of a two-channel multiplexer - inverse output RS- flip-flop, a direct output of which is under way.; to the second control input of the two-channel multiplexer to the inputs of the first and second channels of which are connected, respectively, the outputs of the element-wise reception unit and the element EXCLUSIVE OR, and the editor N.Svydka Order 1139/61 Circulation 624 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Branch ShSh P, tent, Uzhgorod, st. Project, 4 the course of the two-channel multiplexer is connected to the information D-BXO-, an additional K-bit shift register, to the installation R-input of which, as well as to the setting R-inputs of the main K-bit shift register and the RS flip-flop, the output is connected the first element OR, and 10 to the setup S-input of the RS-flip-flop - the output of the last K-bit of the additional K-bit shift register, the outputs of all bits of which are connected to the inputs of the EXTRACT OR OR and the corresponding inputs of the bits of the first comparator number of the digital comparator, to the inputs of the digit The outputs of the second compared number of which are connected to the outputs of the bits of the main K-bit register of the shift. 2. The device POP.1, differing from the fact that the pulse shaper of the initial setting The 5th state contains the D-flip-flop and integrator, the output of which is connected to the installation R-input of the D-flip-flop, the output of which is connected to the input of the integrator and is the output 0 pulse generator set the initial state, the second and third dam of which are appropriately clock setting S - input five , the first-corresponding-C is the input, and the informational D-input of the L-trigger. Compiled by G. Lerantovich Tehred 3. Paliy Proofreader S. Shekmar Subscription