SU657614A1 - Binary counter monitoring device - Google Patents

Description

This invention relates to the field of computing.

A device for controlling a binary counter, a binary counter, OR elements, differentiating chains, delay elements, and a half-adder l, are known.

In the absence of violation and failures, the input signal propagates through a binary counter to trigger T-, which is currently at the o position. and throws

one

From a single

him in position

trigger output using a differentiating chain receives a positive pulse that is applied to the OR element, then the pulse propagates through the error indicator circuit and is fed to the input of a half-adder, to another input of which a signal is received, delayed by a delay element, whose input is connected to the binary counter input, at the time equal to the sum of all the elements of delays. During normal operation of the counter at the output of the half adder, there is no error signal. In case of violation

neither or

on

adder appears error signal.

2

A disadvantage of this device is low reliability.

It is also known a device for controlling a binary counter, which contains an OR element connected through differentiating chains to the outputs of the meter triggers, control triggers and an unequal circuit, one of the counter triggers. The counting input is connected to the output of the OR element, the other trigger is connected to the counter input. , and the outputs of the control triggers are connected to the inequality scheme 2.

B

A disadvantage of this device is that the elements used in the control circuit (trigger trigger) have a low reliability due to the complex circuit construction, which generally reduces the reliability of the control device operation.

The closest in technical essence is a device for controlling a binary counter, containing a binary counter, the input of which is connected to the input of the device, the output of each bit, except for the zero discharge, is connected to the first input of the AND element of this bit, the output of zero discharge connected through

the delay element with the first input output: about the element I, the additional element I Z.

The disadvantage of such a device is that elements (triggers) are used in the control circuit, which themselves require the introduction of additional | because of the complicated circuit construction, in addition, the failure of one of the trigger elements leads to a malfunction of the meter control circuit.

A significant disadvantage of this device; reliability is relatively low.

The purpose of the invention is to increase the reliability and reliability of the binary counter control.

The goal is achieved by the fact that in the control device of a binary counter containing a binary counter, the input of which is connected to the input of the device, the output of each of its discharge, except for the zero discharge, is connected to the first input of the element данного of this discharge, the output of the zero discharge is connected through the element delays with the first input of the output element And, the additional element And, the output of the first and second bits of the binary counter are connected respectively to the first and second inputs of the additional element And, the output of which is connected to the secondary to the inputs of the output element I and the element I of the third discharge, the output of which is connected to the third input of the output element I, the fourth input of which is connected to the output of the element I of the first discharge and to the second input of the element AND of the second discharge whose output is connected to the fifth input the output element And with the third input of the additional element And, the input device is connected to the second input of the element And the first bit, and the output of the output element And is connected to the output of the device.

Figure 1 shows the functional diagram of the device for monitoring a binary counter in relation to the existing system of elements in figure 2 is a timing diagram when the device is working properly; FIG. 3 is a timing diagram in the event of a short refusal of the discharge of the counter.

The device contains AND-H elements 1-5, elements NOT 6-8, delay element 9, counter 10, consisting of binary I-14 cells.

The device works as follows.

The counted pulses with a period of following T from the clock generator are fed to the input 15

the binary cell 11 of the least significant bit of the counter; in this case, the information transmission circuits are monitored by setting the binary cell when the next clock pulse arrives from the clock frequency generator to the next state and the signal is transmitted to the corresponding IS-NOT elements.

The table summarizes the state of the counter before the operation of the account and after it with the marks carried out the transfer or not.

In the initial state, the binary number 0000 is set at all the main outputs of the binary cells 1114 of the counter 10.

When the first clock pulse arrives in binary cells 11-14 of counter 10, binary number 0001 will be written, with this, at the zero-bit output a high level will be present (output 11, figure 2), and the output of the AND-1 element will take place high level (output 1., figure 2), when the second clock pulse arrives in the ll-14i cells of the counter 10, the binary number 0010 is written, while the output of the first bit will contain a high level (output 12, figure 2), and at the output of the element AND-NOT 1 there will be a low level for the duration of the second and third second clock pulses (output 1, FIG. 2) and, finally, when the fifteenth clock pulse arrives at the binary cells 11-14 of the counter 10

the binary number 1111 output 11,12,13,14, Fig. 2) will be written; from the output of the delay element 9 we have a signal (output 9, Fig. 2), which is delayed by the time the counter 10 changes state to inverse, relative to the original condition.

Thus, when the signals coincide (output 1, output 6, output 7, output 8, output 9), the output pulse of the correct operation of the counter 10 (output 16, Fig. 2) will be fixed at output 16 of the NAND element 5,

In case of failure in operation, at least one of the binary cells 11-14, even for a short time, at the output 16 of the element AND-NOT 5, we have a high level. Thus, the impulse of correct operation of the counter is absent for the entire duration of the clock generator, although the failure was short-lived.

In case of a short-term failure, for example, of a binary cell 11, the signals of the control elements do not match, at the outputs of the elements we have: a high level (output 1, fig. 3), a high level (output 6, fig. 3), a low level (output 7 , fig. 3), low level (output 8, fig. 3), from the output of the delay element we have a signal delayed by a time equal to a change in the state of the counter 10 g of the original to inverse (output 9, fig. 3). Thus, we have two mismatch signals: from the output of the element NOT 7 - a low level and from the output of the element NO 8 - a low level; therefore, the error signal - a high level (output 16, fig. 3) to all the clock generator operation time.

The proposed device is characterized by simplicity, high reliability and reliability of control with minimal expenditure on additional equipment for control.

The check of the counter's operation is carried out during the time interval, determined by the delay element and chosen so that during this time the counter reading changes to inverse with respect to the initial state.

Claims (3)

1. Authors certificate of USSR 219897, class, Q 06 F 11/00, 1967. 2. USSR author's certificate number 355746, cl. H 03 K 21/34, 1969. 3. USSR author's certificate number 392502, cl. G 06 F 11/00, 1971. breathing IS