SU434609A1 - DEVICE FOR THE CONTROL OF CLOCK SYNCHRONIZATION - Google Patents

Description

one

The invention relates to telecommunications, for example, can be used to monitor the cyclic failure of clock synchronization devices of data transmission systems.

According to the main author. St. 391,751 A device for monitoring clock synchronization is known, in which, at the beginning of each cycle of the measurement determined by the meter installation signal of the gate number meter, the measurement gate signal coinciding in time with the meter installation signal is lost, which leads to a decrease in the accuracy and reliability of the device. in work.

The purpose of the invention is to improve the accuracy and reliability of the device in operation.

The goal is achieved by the fact that the output of the pulses of the sensor installation of the reference signals is connected to the counting input of the counter of the gate number meter through the first additional circuit AND, and to the single input of the first digit of the counter, through the series-connected inverter, the second additional circuit And and the trigger , to the zero input of which the clock is connected - the output of the sensor of the reference signals, in addition, both additional circuits And are controlled from the output of the clock synchronizer.

FIG. 1 shows the block diagram of the proposed device to control the clock synchronization; in fig. 2 - timing diagram of the counter meter of the number of gates. The device consists of a clock synchronizer 1, a counter 2, a meter for the number of strobes, a reversible counter 3, a simulator of receiver 4, a sensor 5 of reference signals, a latch 6 of zero error, a decoder 7, a delay line 8, an AND 9 circuit, a cyclic failure indicator 10, an inverter 11 ,

trigger 12 and schemes “And 13 and 14.

Counter 2 operates as follows. The reset signal of counter 2 is prohibiting pulses from an AND 13 circuit.

the counting input of counter 2. As the signal of the setup goes to the input of another circuit AND through the inverter 11, for this circuit the setup signal is enabling. Therefore, the counting pulses are passed on

input of counter 2 only when there is no installation signal.

The installation signal sets the number of strobes to the zero state. With the coincidence of the counting pulse with

By the setting signal, a counting pulse through the circuit & 14 sets the trigger 12 to one state. The trigger 12 is designed to memorize the counting pulse, which coincides with the setup signal, since

the installation signal counter 2 is held in

zero state. At the end of the setup signal, a signal from the output of the trigger 12 is written to the unit in the first bit of counter 2. Following this clock signal, coming from the output of the reference signal sensor 5, the trigger 12 returns to the nervous state.

Subject invention

The device control clock synchronization auth. St. 391751, characterized in that, in order to increase the accuracy and reliability of the device in operation, the output of the sensor pulses of the reference signal sensor is connected to the counting input of the meter of the number of gates through the first complementary circuit "And, and to the single input of the first digit of the mentioned counter - through Inverter connected in series, second And additional circuit and trigger, to the zero input of which the clock output of the reference signal sensor is connected, besides, both And additional additional circuits are controlled from the clock syn ronizatora.

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