SU1246047A1 - Electronic timepiece - Google Patents

Abstract

This invention relates to a digital watch with a digital display and increases its accuracy. The clock contains a generator of I pulses, a divider 2 frequencies, a counter 3 and a counter 4 minutes, a counter 5 hours, a synchronization unit 6, a reversing counter 7, elements AND 8 and 9, a sign of 10 hours difference, an adjustment unit II, a delay element 13 and elements OR 14 and 15. The introduction of new delay elements 13 and the SHSh 15 element and the formation of new connections between the elements of the device make it possible to increase the accuracy of the device without increasing the frequency of the master oscillator. 1 il. (L od od o 4

Description

This invention relates to an electronic watch with a digital display.

The aim of the invention is to improve the accuracy of the clock by reducing the step of adjusting their stroke,

The drawing is a diagram of the clock.

The clock contains 1 generator of J frequencies and 2 frequencies, which is a scaling circuit with an error output, a counter for 3 seconds and a counter for 4 hours, a counter for 5 hours, a synchronization unit 6, a reversible counter 7, and 8 and 9 elements that make up block 10 determining the sign of the divergence of the clock 5, the adjustment block 11 containing n elements AND 12 - 12j and the delay element 13, as well as the elements OR 14 and 15.

The output of the clock synchronization unit 6 is connected to the inputs to setting the zero frequency divider 2, the counter 3 seconds and the counter 4 minutes and the first inputs of the And 8 and 9 J elements whose second inputs are connected

respectively to the forward and inverse 25 (;; s of generator 1 are such that by the output of the highest discharge of the counter 4 minutes and outputs respectively to the summing and subtracting inputs of the reversing counter 7, the output of the i-ro pulse input to the second input of the element OR 15 transitional The processes in the 2 frequency divider end,

where and where

1, 2 ,,,,, p, is connected to the first input of the And 12 i element of the control unit II, the second inputs of the And 12 elements of which j where, j - 2, 3, „, n, are connected to the output of the counter for 3 seconds.

The first and second inputs of the element OR 14 are connected respectively to the output of the counter 4 blinking and the output of the element AND 8 ,, The output of the element OR 14 is connected to the input of the counter 5 hours

Pulse generator. connected to the first input of the element OR 15 whose output is connected to the input of the splitter 2 frequency. The output of the counter 3 seconds is connected to the input of the delay element 13, the output of which is connected to the second input of the element 12, the control unit 11. The output of the first digit of the counter 4 minutes is connected to the third input of the element 12 of the control unit 11, the output of which is connected to the second input of the element 11PI 15. The output 12 of the control unit 1I is connected to the input of the unit in state one (j.-l) .- ro bit divider 2 frequencies.

The pulses work as follows. The pulses from the generator 1 are filled through the element OR 15 divider 2 frequencies and then the counter is 3 seconds. An overflow pulse from the counter output of 3 seconds enters the counter input for 4 minutes and the inputs of the And 12f 12j elements of the control unit 11. At the same time, the contents of the 2-p counter 7 are rewritten into the 2 frequency divider. At the same time, the period duration

which is in the counter

The seconds recorded are zero, less than one second.

If in the low-order discharge of the counter 4 minutes is one, then through the delay element 13, the element 12 and the element 15 will overflow the pulse from the output of the counter for 3 seconds to the input of the divider 2 frequency.

The low-order counter 3 minutes switches on one of the edges of the pulse, such as back, and the time 13 of the delay and the duty cycle

At the moment when the pulse arrives at the second input of the element OR 15, the transients in the frequency divider 2 end,

Thus, the low spacing value of the counter 7 is added to the contents of the divider 2 frequencies every odd minute, i.e. the weight of one step of adjustment determined

The meter low of counter 7 corresponds to half the period of the clock frequency of generator I.

After the clock has become unacceptably large, the owner corrects them, for example, presses the button at the time of transmitting the exact time signals. At the same time, the impulse from the synchronization block b is applied to the elements 8 and 9 of block 10

determine the sign of the clock.

If the clock for the period elapsed from the previous correction went ahead, then in the highest order of the counter 4 minutes - zero (for example, I 2 h 00 1.shn

About c) o And this case is a signal from

the synchronization unit 6 will go through the element E to the subtracting input of the reversible counter 7; As a result, the result contained in the counter 7,

will decrease, the duration of the period at which a zero value in the 3 seconds counter will increase and the clock will slow down will increase. With the same signal from synchronization unit 6, the divider 2 frequencies, the counter 3 seconds and the counter 4 minutes are zeroed.

If, for the period that has passed from the previous correction, the clock is lagging behind, then in the highest discharge of the counter, 4 minutes is one (for example, P h 59 min 59 s). In the 3TOMi case, the signal from the synchronization unit will go through AND 8 to the summing input of the reversible counter 7. As a result, the number contained in counter 7 increases, the duration of the period at which a zero value is recorded in the counter for 3 seconds, and the clock accelerates.

The same signal from synchronization unit 6 included a divider 2 frequencies, a counter of 3 seconds and a counter of 4 minutes, and to the contents of the counter of 5 hours through the OR element. 14 unit will be added.

The capacitance of the counter 7, divider 2 frequencies and the frequency of the generator 1 are chosen such that, with a given error of the frequency of the generator 1, to compensate for any possible frequency drift.

Thus, the accuracy of the movement of the clock is increased, as the pitch decreases, by which the control of the movement of the clock is possible. An increase in accuracy is achieved by introducing a delay element and an OR element, without increasing the frequency of the master oscillator.

Claims (1)

Invention Formula An electronic clock containing a pulse generator, a serially connected frequency divider and counters of seconds, minutes and hours, a synchronization unit, a reversible counter, the first and second elements AND, the first, the OR element, and the control unit. Compiled by S. Shakin Editor N, Egorova Tehred I.Popovich Proofreader M, Sharoshi 3997/39 Circulation 398 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Proizvodstvon 1-printing company, Uzhgorod, st. Project, 4 ten 15 40047 containing n elements AND by the number of bits of the reversible counter, njJH- than the output of the synchronization unit is connected to the inputs of the installation in zero compositing of the frequency divider and seconds and minutes counters and to the first inputs of the first and second elements AND, the second inputs of which are connected respectively to the direct and inverse outputs of the higher bit of the minutes counter, and the outputs of the first and second elements AND are connected respectively to the summing and subtracting inputs of the reversing counter, the output of the 1st bit of which, where 1 I, 2 is n, is connected to the first the input of the i-ro element And the control unit, the second inputs j-x. elements And whose, where j 2, 3, .., p, are connected to the counter output of the second, the first and second inputs of the first element OR are connected respectively to the output of the counter and the output of the first element AND, and the output of the first element OR is connected to the input of the hour counter, which is different in order to increase the accuracy hours by reducing the step of adjusting their stroke, a second OR element is inserted in them, and a delay element is inserted into the control unit, the output of the pulse generator connected to the first input of the second OR element, whose output is connected to the input of a frequency splitter The seconds counter is connected to the input of the delay element, the output of which is connected to the second platoon of the first element I of the control unit, the output of the first discharge of the counter is connected to the third input of the first element I of the control unit whose output is connected to the second input of the second element OR , the output of the j-ro element And the control unit is connected to the input of the unit in a single state (j -) - ro bit of the frequency divider. 25 thirty five 0 five