JPH0616358Y2 - World clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a world timepiece having a plurality of display timepieces for simultaneously displaying the time in various parts of the world based on the time signal of one reference timepiece.

[Prior Art] Today, for example, world clocks that display time around the world by combining a world map and a plurality of clocks are increasing.

In this way, as a world clock that simultaneously displays the local time of each place by multiple clocks, each clock separately and independently clocks the time and displays the time. Clocks are added together with the time of each place, and the reference time data and the time data of each place are sent from this reference clock to each display clock, whereby the time is displayed on each display clock, and each clock is independent. The time difference of each clock is corrected by the signal from the reference clock while performing the clocking (for example, No. 62-141.781 of Shokai Kai).
Etc. There are various types.

[Problems to be Solved by the Invention] As described above, the world clock uses a plurality of display clocks to display different times, but the region to be displayed and the number of display clocks differ depending on the customer's request. It is a thing.

A world clock in which each clock independently counts time has wide freedom in setting the number of display clocks and time difference, but the clocking error must be corrected for each clock. It takes time to maintain and correct the clock, and
Since it requires a large number of watches, it has the drawback of being expensive.

In addition, since the display area is determined by the time difference data setting, the world clock that measures the time of each place by adding the reference time and the time difference data by the reference clock determines the number of display clocks and the time difference for each world clock with a different display area. Since it is necessary to set the data, it is difficult to uniformly mass-produce the world timepiece, and the wiring from the reference timepiece to each display timepiece is complicated.

Furthermore, each of the display clocks which receives the correction signal of the error from the reference clock while independently measuring the time is relatively expensive because it requires a plurality of clocks, and the time difference is calculated in the reference clock. Therefore, since the correction signal is output from the reference clock at each required time, the output time of the correction signal must be set for each world clock with different display clocks and display areas,
It was not suitable for mass production.

[Means for Solving the Problems] A reference clock circuit that measures a time and outputs a start signal, a minute reference signal, and a time reference signal; and a clock signal, a minute control signal, and a clock signal for a required time when the start signal is input. A timing control circuit that outputs an hour control signal, a minute reference signal is read by a start signal, and the minute reference signal and a signal having a value obtained by sequentially adding a predetermined value to the value of the minute reference signal are used as the minute signals of the serial signal. An auxiliary minute counter circuit that sequentially outputs and outputs a minute block signal every time one value is output, and an hour reference signal is read by a start signal, and an hour reference signal and a value obtained by sequentially adding 1 to the hour reference signal. Of the auxiliary signal and the auxiliary block counter circuit that outputs the hour block signal each time one value is output, and the minute block signal or the hour block signal. A timing signal output circuit for outputting the clock signal as a timing signal,
When a minute block signal and a minute control signal are input, a fractional-division circuit that outputs a fractional-division signal that advances the count value of the auxiliary minute-counter circuit, and a data output circuit that outputs the minute-signal or hour signal as a data signal, A data signal, a timing signal, and a clock signal are input, and a world clock is configured by a plurality of display clock units that display time by minute signals and hour signals of required values among the data signals.

[Operation] The present invention measures the reference time by the reference clock circuit and outputs the minute reference clock and the hour reference signal, and the auxiliary minute counter circuit sequentially adds a constant numerical value as a time difference to the minute signal. This auxiliary signal is sequentially output from the auxiliary minute counter circuit as a serial signal, and the auxiliary time counter circuit sequentially adds 1 to the hour reference signal to generate a time signal. This time signal is sequentially output from the auxiliary time counter circuit. , And the minute block signal is output each time one numerical value minute signal is output as a serial signal, and the hour block signal is output each time one numerical value hour signal is output as a serial signal. ,or,
A clock signal is output from the timing control circuit, and a time control signal and a minute control signal for a certain period are output.
When the hour control signal is output, the timing signal output circuit passes the hour block signal as the timing signal, and
The data output circuit can pass the hour signal as the data signal, and when the timing control circuit outputs the minute control signal, the timing signal output circuit passes the minute block signal as the timing signal and the data output circuit passes the minute signal. The signal can be passed as a data signal, and the fractional-division circuit outputs a fractional-division signal that increments the count value of the auxiliary minute counter circuit by a constant number each time the minute block signal is output.

Further, the data signal is sent to the display clock unit, and the display clock unit reads only the minute signal and the hour signal of a specific numerical value based on the timing signal, and displays the time by the minute signal and the hour signal on the display unit.

[Embodiment] In the embodiment according to the present invention, as shown in FIG. 1, a reference clock circuit 10 in which a reference signal output terminal of an oscillation circuit 12 is connected to a minute counter 16 and an hour counter 18 via a frequency dividing circuit 14 is provided. The reference clock circuit 10 sends the count value signal of the minute counter 16 and the count value signal of the hour counter 18 to the plurality of display clock units 86 via the signal output circuit 22.
Is a crystal oscillator built-in, which outputs a highly accurate reference signal, and this reference signal is appropriately divided by the frequency dividing circuit 14,
The minute counter 16 and the hour counter 18 count clocks by dividing the reference signal, and the minute counter 16 outputs this count value as an 8-bit parallel minute reference signal, and the hour counter 18 counts it. The value is output as a reference signal when 5 bits are parallel. The correction circuit 20 is a circuit for correcting the time measurement error in the minute counter 16 and the hour counter 18.

The signal output circuit 22 receives from the minute counter 16 the minute reference signal that is the Y signal that is paralleled to 8 bits, and the auxiliary minute counter circuit 36 that outputs the time reference signal that is the Z signal that is paralleled to 5 bits to the hour counter 18. It is composed of an auxiliary counter circuit 46 received from the other, a timing control circuit 24 and the like.

As shown in FIG. 2, the timing control circuit 24 includes two OR circuits, one inverter and an AND circuit, and 37
1-bit Johnson to 24-bit output of the timing signal output circuit 70, which will be described later, to the input terminal of the first Johnson counter 28 via the first inverter 26. The terminals are grouped into one by a first OR circuit 30 which is a 24-input OR circuit, and the output terminals of the first OR circuit 30 are a timing signal output circuit 70 and a data output circuit 78, which will be described later, and a first Johnson counter 28. The 25th to 36th bit output terminals of are integrated into one by the second OR circuit 32 which is a 12-input type OR circuit, and the output terminal of the second OR circuit 32 is described later in the division circuit 5
6, connected to the timing signal output circuit 70 and the data output circuit 78, the 37th bit output terminal is connected to the negative input terminal of the first AND circuit 34 which is a 2-input AND circuit, and the other of the first AND circuit 34. A normal input terminal which is an input terminal is connected to _one reference signal output terminal of the frequency dividing circuit 14 in the reference clock circuit 10, and an output terminal of the first AND circuit 34 is connected to a display clock section 86 which will be described later and will be described later. Auxiliary counter circuit 36
And the auxiliary counter circuit 46, and the reset terminal of the first Johnson counter 28 is connected to the _three reference signal output terminals of the frequency dividing circuit 14 in the reference clock circuit 10.

This Johnson counter sets any one of the output terminals to the H level, sets the first bit output terminal to the H level in the reset state, and thereafter, when a clock signal is input to the input terminal, one pulse of the clock input is input. The output terminal for sequentially outputting the H level signal is sequentially switched from the first bit output terminal to the second bit output terminal and the third bit output terminal every time.

Therefore, when the start signal of the H pulse is output to the _three reference signals which are the A signals, the timing control circuit 24 sets the first bit of the first Johnson counter 28 to the H level by the start signal. The counter 28 is reset, the control signal is output to the B signal which is the output of the first OR circuit 30 when it is at the H level, the first AND circuit 34 is opened, and the _first reference signal from the frequency dividing circuit 14 is used as the clock signal. The 1 AND circuit 34 outputs the E signal. And the first
When the H pulse timing signal is input to the input terminal of the Johnson counter 28, the output of the H level signal is sequentially moved to the second bit output terminal and the third bit output terminal for each pulse of the timing signal, and the timing signal is output. As 24
The control signal is output from the first OR circuit 30 when it is at H level while 12 pulses are input, and the H level is output from the second OR circuit 32 while 12 pulses are input from the 25th pulse. The control signal is output to the C signal, the first AND circuit 34 is closed by the 37th pulse input, and the output of the clock signal is stopped. It should be noted that the first inverter 26 has an H level in the timing signal.
1st Johnson counter 28 in synchronization with the trailing edge of the pulse
This is for progressively advancing the output terminals for outputting the H level.

The auxiliary minute counter circuit 36 includes a presettable counter, a Johnson counter, an AND circuit, and an OR circuit. The data input terminal of the second minute counter 38, which is a presettable counter, has a minute counter 16 in the reference clock circuit 10. The second minute counter connected to the data output terminal of
The load terminal of 38 is the second terminal of the auxiliary counter circuit 36.
It is connected with the reset terminal of the Johnson counter 40 to the _three reference signal output terminals of the frequency dividing circuit 14 in the reference clock circuit 10, and the second Johnson counter 40 uses a 9-bit Johnson counter which is one bit larger than the number of bits of the minute reference signal. , The first to eighth bits of the second Johnson counter 40
The bit output terminal is connected to one input terminal of each AND circuit of the first AND circuit group 42 composed of eight AND circuits, and the ninth bit output terminal is connected to a timing signal output circuit 70 and a fractional circuit 56 described later. Connecting. The other input terminal of each AND circuit in the first AND circuit group 42 is the second minute counter 38.
Are sequentially connected to the data output terminals of the first AND circuit group 42, and the output terminals of the respective AND circuits in the first AND circuit group 42 are combined into one by the third OR circuit 44 which is an 8-input type OR circuit.
Is connected to a data output circuit 78 described later, the input terminal of the second minute counter 38 is connected to the fractional circuit 56 described later, and the input terminal of the second Johnson counter 40 is connected to the first timing control circuit 24. Connect to the output terminal of the AND circuit 34.

Therefore, in the auxiliary minute counter circuit 36, when the H pulse start signal is output to the A signal, the second minute counter 38 causes the minute counter in the reference clock circuit 10 by the start signal.
The count value of 16 is preset, and the second Johnson counter 40 is reset by the start signal. Then, the timing control circuit 24 is added to the second Johnson counter 40.
The second Johnson counter 40 changes the output terminal for outputting the H level sequentially from the first bit output terminal to the ninth bit output terminal when the clock signal from the first bit to the eighth bit output terminal is input. The AND counters of the first AND circuit group 42 are opened one by one in response to the output signal from the minute AND counter 16 preset in the second minute counter 38.
The 8-bit signal which is the count value of the third OR circuit
44, and thereby the minute reference signal which is an 8-bit parallel signal is converted into an 8-bit serial minute signal to convert the third OR circuit.
It outputs to the F signal which is the output of 44 and outputs from the third OR circuit 44 to 8
The second Johnson counter after outputting the bit signal
The H pulse from the ninth bit output terminal of 40 is output as the minute block signal to the G signal, and the minute block signal is sent to the timing signal output circuit 70 and the fractional advance circuit 56, and the second pulse is again output.
The output of the value of the minute counter 38 from the third OR circuit 44 as the minute signal of the serial signal is repeated. And the second
When the minute counter signal from the minute counter circuit 56 is input to the minute counter 38, the second minute counter 38 sets the value obtained by adding the number of pulses of the minute counter signal to the value of the preset minute reference signal as It outputs a new value as a split signal,
Each time the fractional signal is input to the second minute counter 38, the count value is sequentially increased, and this value is output from the third OR circuit 44 as an 8-bit parallel minute signal and the ninth bit of the second Johnson counter 40 is output. The output of the minute block signal from the output terminal is repeated.

Also, the auxiliary time counter circuit 46 is substantially the same as the auxiliary minute counter circuit 36, and the presettable counter is used as the second time counter 48, and since the time reference signal is a 5-bit parallel signal, a 6-bit Johnson counter is used. A third Johnson counter 50, wherein the first to fifth bit output terminals of the third Johnson counter 50 are connected to the input terminals of the respective AND circuits of the second AND circuit group 52 composed of five AND circuits, The other input terminal of each AND circuit in the second AND circuit group 52 is connected to the data output terminal of the second time counter 48, and all the output terminals of the second AND circuit group 52 are connected to the fourth output terminal.
The output circuit of the fourth OR circuit 54 is connected to a data output circuit 78 described later, and the data input terminal of the second hour counter 48 is the data output terminal of the hour counter 18 in the reference clock circuit 10. The load terminal of the second hour counter 48 is connected with the reset terminal of the third Johnson counter 50 to the _three reference signal output terminals of the frequency dividing circuit 14 in the reference clock circuit 10, and the sixth bit output terminal of the third Johnson counter 50 is connected. Is connected to the input terminal of the second hour counter 48 and is connected to the timing signal output circuit 70 described later, and the input terminal of the third Johnson counter 50 is connected to the output terminal of the first AND circuit 34 in the timing control circuit 24. .

Therefore, in the auxiliary time counter circuit 46, when the start signal is input, the count value of the hour counter 18 is preset in the second time counter 48 by the 5-bit parallel time reference signal, and the third Johnson counter 50 is simultaneously reset. Therefore, the third Johnson counter 50 sequentially outputs the H level signal from the first bit output terminal by the clock signal from the timing control circuit 24, and the second time counter is output by the H level signal of the first to fifth bit output terminals. The count value of 48 is output to the H signal which is the output of the fourth OR circuit 54 as a 5-bit serial signal, and the 5-bit serial signal is output from the fourth OR circuit 54. By setting to H level, the block signal is output to the I signal at the time of H pulse, and the second time count is made by the block signal at the time of H pulse. With increasing by one the count value of 48, when the block signal timing signal output circuit
Send to 70. Then, the new count value of the second hour counter 48 is output from the fourth OR circuit 54 as a 5-bit serial time signal, the hour block signal is further output, and the count value of the second hour counter 48 is incremented by 1 again. Repeat that.

The fractional-division circuit 56 is composed of three AND circuits, two inverters, and a 5-bit Johnson counter, and the ninth bit output terminal of the second Johnson counter 40 in the auxiliary minute counter circuit 36 is connected to the second AND circuit. The input terminal of the circuit 58 is connected to the reset terminal of the fourth Johnson counter 66 via the third inverter 68, and the other input terminal of the second AND circuit 58 is connected to the second OR circuit 32 of the timing control circuit 24. Connected to the output terminal, the second AND circuit 58
Is the input terminal of the third AND circuit 60, the other input terminal of the third AND circuit is the ₀ reference signal output terminal of the frequency divider circuit 14 in the reference clock circuit 10, and the output terminal of the third AND circuit 60 is The other input terminal of the fourth AND circuit 62 is connected to the fifth bit output terminal of the fourth Johnson counter 66 as the negative input type, and the output terminal of the fourth AND circuit 62 is connected to the input terminal of the fourth AND circuit 62. It is connected to the input terminal of the fourth Johnson counter 66 via the two inverters 64 and to the input terminal of the second minute counter 38 in the auxiliary minute counter circuit 36.

The ₀ reference signal is a pulse signal having a frequency about 10 times that of the ₁ reference signal.

In the fractional circuit 56, the timing control circuit 24 outputs the C signal to the H level.
When the second Johnson counter 40 in the auxiliary minute counter circuit 36 outputs the H pulse minute block signal while the level minute control signal is being output, the second minute counter signal is output only while the minute block signal is being output. The output of the AND circuit 58 is set to the H level, the third AND circuit 60 is opened, and the ₀ reference signal is output from the output terminal of the third AND circuit 60. At this time, the minute block signal is output via the third inverter 68. Since the reset signal is input to the reset terminal of the fourth Johnson counter 66, the reset state of the fourth Johnson counter 66 is released by the minute block signal, and thus the ₀ reference signal that has passed through the fourth AND circuit 62 is used as a fractional signal for the auxiliary division. Not only is it sent to the second minute counter 38 in the counter circuit 36, but also to the fourth Johnson counter 66 in the minute advance circuit 56.
_{When the zero} reference signal is sent and the fourth AND circuit 62 passes five pulses of the _zero reference signal, the fifth bit output terminal of the fourth Johnson counter 66 becomes H level and the fourth AND circuit
It is a fractional signal to the auxiliary minute counter circuit 36 by closing 62.
_When the output of the ₀ reference signal is stopped and then the output of the minute block signal is stopped and the G signal returns to the L level, the fourth Johnson counter 66 is reset and the fifth bit output terminal returns to the L level. Therefore, the fractional-division circuit 56 outputs five pulses to the second minute counter 38 every time the minute block signal is output.
Is output to.

The timing signal output circuit 70 has two AND circuits and one
The input terminal of the fifth AND circuit 72 is the second Johnson counter in the auxiliary counter circuit 36.
Connected to the output terminal of the second OR circuit 32 in the timing control circuit 24 and the input terminal of the sixth AND circuit 74 is the sixth bit of the third Johnson counter 50 in the auxiliary counter circuit 46. The output terminal is connected to the output terminal of the first OR circuit 30 in the timing control circuit 24, and the output terminal of the fifth AND circuit 72 and the output terminal of the sixth AND circuit 74 are connected to the input terminal of the fifth OR circuit 76. The output terminal of the fifth OR circuit 76 is connected to the later-described display clock section 86 and also to the timing control circuit 24 as described above.

Therefore, when the minute control signal is input, the timing signal output circuit 70 opens the fifth AND circuit 72 to output the minute block signal as the timing signal to the M signal which is the output of the fifth OR circuit 76, and also for the time control. When the signal is input, the sixth AND circuit 74 is opened to output the time block signal as the timing signal to the M signal which is the output of the fifth OR circuit 76, and the timing signal is sent to the timing control circuit 24 and the display clock section 86. It is what is output.

The data output circuit 78 is also composed of two AND circuits and one OR circuit. The input terminal of the seventh AND circuit 80 is the output terminal of the third OR circuit 44 in the auxiliary minute counter circuit 36 and the timing control circuit 24. It is connected to the output terminal of the second OR circuit 32, and the input terminal of the eighth AND circuit 82 is the output terminal of the fourth OR circuit 54 in the auxiliary counter circuit 46 and the output terminal of the first OR circuit 30 in the timing control circuit 24. And an output terminal of the seventh AND circuit 80 and an eighth AND circuit
The output terminal of 82 is connected to the input terminal of the sixth OR circuit 84, and the output terminal of the sixth OR circuit 84 is connected to a display clock section 86 described later.

Therefore, the data output circuit 78 opens the seventh AND circuit 80 when the minute control signal is input to pass the minute signal from the auxiliary minute counter circuit 36, and opens the eighth AND circuit 82 when the hour control signal is input. The hour signal from the auxiliary counter circuit 46 is passed therethrough, and the minute signal or the hour signal is output from the sixth OR circuit 84 to the P signal as a data signal.

The overall operation of the signal output circuit 22 configured as described above is performed by setting the _three reference signals, which are start signals, to 1/60 Hz, and the minute reference signal from the minute counter 16 and the hour counter 18 from the minute counter every one minute. The hour reference signal is preset in the second minute counter 38 in the auxiliary minute counter circuit 36 and in the second hour counter 48 in the auxiliary minute counter circuit 46, and the start signal causes the second Johnson counter 40 in the auxiliary minute counter circuit 36 and the auxiliary hour counter 48 to be preset. The third Johnson counter 50 in the counter circuit 46 and the first Johnson counter 28 in the timing control circuit 24 are reset. Therefore, the timing control circuit 24 starts outputting the clock signal and outputs the hour control signal, and the time control signal opens the sixth AND circuit 74 in the timing signal output circuit 70 and the eighth AND circuit 82 in the data output circuit 78. . Then, in response to the clock signal from the timing control circuit 24, the auxiliary counter circuit 46 outputs the 5-bit time signal from the fourth OR circuit 54 to H level.
The signal is output as a data signal from the data output circuit 78 to the P signal at this time, and the hour block signal is output as the I signal every time a 5-bit data signal is output.
The count value of the second hour counter 48 is incremented by 1, and
At that time, the block signal passes through the timing signal output circuit 70 to be a timing signal, and the output terminal for outputting the H level of the first Johnson counter 28 in the timing control circuit 24 is switched to the second bit output terminal. The count value of the counter 48 is output as a 5-bit serial time signal, that is, a data signal, the count value of the second time counter 48 is incremented by 1, and the H level output terminal of the first Johnson counter 28 is incremented by 1 repeatedly. , When the 24 hour block signals are output, the count value of the second hour counter 48 is added by 24 (decimal number) and makes one round. At this time, the first Johnson counter 28 in the timing control circuit 24 outputs the 25th bit terminal. As the H level, the second OR circuit 32 outputs the H level control signal, and the output of the hour control signal is stopped. Therefore, in the timing signal output circuit 70, the sixth AND circuit 74 is closed and the fifth AND circuit 72 is opened, and in the data output circuit 78, the eighth AND circuit 82 is closed and the seventh AND circuit 80 is opened, and the data output circuit 78 is opened. Means that the minute signal output from the auxiliary minute counter circuit 36 is output as a data signal. When the value of the minute counter 16 preset in the second minute counter 38 is output as an 8-bit serial minute signal, the auxiliary minute counter circuit 36 outputs a minute block signal, advances the H level output terminal of the first Johnson counter 28 in the timing control circuit 24 by one, and opens the first AND circuit 58 and the second AND circuit 60 in the fractional progression circuit 56. The J signal is made to output 5 pulses as a fractional signal, and the count value of the second minute counter 38 is incremented by 5 by this fractional signal, which is 5 (decimal number) than the value of the minute counter 16. Value is output again as an 8-bit serial minute signal, and the minute signal having a value increased by 5 is outputted 12 times. The minute block signals output during this time are sequentially output to the timing control circuit 24 as 12 timing signals. Entered, the 1st Johnson counter 28th
The 37-bit terminal output outputs an H level signal to close the first AND circuit 34, stop the output of the clock signal, and stop all the operations of the signal output circuit 22.

Therefore, the signal output circuit 22 reads the count values of the minute counter 16 and the hour counter 18 in the reference clock circuit 10 every one minute, and the data signal which uses the count value of the hour counter 18 and the value obtained by sequentially adding 1 as the hour signal. Is output 24 times, then the count value of the minute counter 16 and a value obtained by sequentially adding 5 are output 12 times, and the data signal is stopped.
Assuming that _one reference signal from the frequency dividing circuit 14 is a reference signal of 1 KHz, for example, all time data can be output in 5 minutes for 24 hours in about 0.25 seconds.

Each display clock unit 86 comprises a 37-bit Johnson counter, two NAND circuits, a shift register, a latch circuit, a decoder driver and one display unit as shown in FIG. Johnson Counter 88 1st
Either the bit output terminal to the 24th bit output terminal
Connect one of the 25th bit output terminal to the 36th bit output terminal to the 1 input terminal of the first NAND circuit 90 to the 1 input terminal of the NAND circuit 92, and connect the output terminal of the 1st NAND circuit 90 to the 8-bit serial input terminal. Parallel-out first shift register 94
The output terminal of the second NAND circuit 92 is connected to the input terminal of the second shift register 86 of 5-bit serial in parallel out.
Connected to the input terminal of the first shift register 94, and the data output terminal of the first shift register 94 is connected to the data input terminal of the first latch circuit 98.
The data output terminal of the shift register 96 is the second latch circuit 10
0 is connected to the data input terminal, and the load terminal of the first latch circuit 98 and the load terminal of the second latch circuit 100 are both the fifth terminal.
Connect to the 37th bit output terminal of Johnson Counter 88,
The output terminal of the first latch circuit 98 is the first decoder driver 10
The output terminal of the second latch circuit 100 is also connected to the display section 106 via the second decoder driver 104, and the input terminal of the fifth Johnson counter 88 in the display clock section 86. To the timing signal output circuit 70, each of the first NAND circuit 90 and the second NAND circuit 92.
First AND circuit of timing control circuit 24 with input terminals
34 includes a first shift register 94 and a second shift register 96.
The respective data input terminals of are connected to the data output circuit 78. The fifth Johnson counter 88 resets the signal from the 37th bit output terminal through the delay circuit 97.

In the display clock unit 86, since one input terminal of the second NAND circuit 92 is connected to any of the first to 24th bit output terminals of the fifth Johnson counter 88, the first pulse as the timing signal Connected 5th of 24th pulse
The second NAND circuit 92 is opened only for one pulse period in which the output terminal of the Johnson counter 88 is at H level, and only at this time, the clock signal from the timing control circuit 24 is input to the input terminal of the second shift register 96. The 5-bit time signal output to the P signal as the data signal is stored in the second shift register 96. Also, the first NAND circuit 90
Is connected to any one of the 25th to 36th bit output terminals of the fifth Johnson counter 88, the first output terminal of the connected fifth Johnson counter 88 is set to the H level for a period of one pulse. 1 NAND circuit 90 is opened,
Only at this time, the clock signal from the timing control circuit 24 is input to the input terminal of the first shift register 94, and the 8-bit sub-signal output as the data signal at this time is stored in the first shift register 94. Then, when the 37th H pulse is output to the P signal as the timing signal, the fifth Johnson counter 88 outputs the H level signal to the 37th bit output terminal, and the storage value of the first shift register 94 is changed to the first latch circuit. Then, the value stored in the second shift register 96 is latched in the second latch circuit 100. Therefore, the values latched by the first latch circuit 98 and the second latch circuit 100 are displayed on the display unit 106 by passing through the first decoder driver 102 and the second decoder driver 104.

Therefore, the world clock in this embodiment is the first NAND circuit 90.
1 input terminal of the fifth Johnson counter 88
Select which of the 24-bit output terminals to connect to, and connect one input terminal of the second NAND circuit 92 to the fifth Johnson counter.
By selecting which of the 25th to 36th bit output terminals of 88 is connected, it is possible to freely display the reference time and the time of each place according to the time difference of 5 minutes in the display clock section 86. Since the input terminals of each display clock unit 86 are connected in parallel and connected to the data output circuit 78, the timing signal output circuit 70, and the timing control circuit 24 in the signal output circuit 22,
The number of display clock parts 86 can be freely determined.

[Advantage of the Invention] Since the world timepiece according to the present invention has only one reference timepiece circuit as a timepiece, it is inexpensive and the correction of the timing error is extremely easy, and in the signal output circuit. The auxiliary minute counter circuit and the auxiliary time counter circuit can equally divide 24 hours and output many hour signals and minute signals having various time differences as data signals.

Since the data signal is output as a serial signal through one signal line, there are three signal lines: a signal line from the data output circuit, a signal line from the timing signal output circuit, and a signal line from the timing control circuit. Wiring to the display clock unit is simple because the display clock unit can be provided in parallel because it is only wired to the display clock unit provided with a large number of signal lines. Furthermore, many hour signals and minute signals are output. Since the signals are output from the circuit, the number of display clock parts and regions can be freely determined, and world clocks can be mass-produced at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing an entire circuit of a world timepiece according to the present invention, FIG. 2 is a diagram showing an embodiment of a signal output circuit, FIG. 3 is a diagram showing a circuit example of a display clock unit, and FIG. It is a time chart figure showing the signal of a signal output circuit. 10 …… reference clock circuit, 16 …… minute counter, 18 …… hour counter 18, 22 …… signal output circuit, 24 …… timing control circuit, 36 …… auxiliary minute counter circuit, 46 …… auxiliary hour counter circuit, 56 …… Diversion circuit, 70 …… Timing signal output circuit, 78…
… Data output circuit, 86… Display clock section.

Claims (1)

[Scope of utility model registration request] 1. An oscillator circuit for outputting a reference signal and a frequency divider circuit for dividing the reference signal from the oscillator circuit are built-in, and the reference signal divided by the frequency divider circuit is counted by a minute counter and an hour counter. Output the division reference signal and the hour reference signal, and the reference clock circuit that outputs a start signal of a constant cycle from the frequency divider circuit, and the clock signal is output by the start signal, and the timing signal described later is input. Then, the hour control signal is output for the required time based on the timing signal, the minute control signal is output for the required time when the hour control signal is not output, and the hour control signal or the minute control signal is output. The timing control circuit that maintains the output of the clock signal for a period of time, and the minute reference signal from the minute counter is read by the start signal, and the minute reference signal is read by the clock. Signal is output as a minute signal that is a serial signal synchronized with the signal, and the value obtained by sequentially adding a predetermined value to the value of the minute counter is also sequentially output as a minute signal of the serial signal. An auxiliary minute counter circuit that outputs a minute block signal each time it finishes outputting, and a time reference signal from the hour counter is read by a start signal, and this time reference signal is output as a time signal that is a serial signal synchronized with the clock signal. In addition, the auxiliary time counter outputs the hour block signal each time the serial signal outputs one value by repeating the sequential output of the value obtained by adding 1 to the value of the hour counter as the serial time signal. A circuit, the minute block signal and the hour block signal, the minute control signal and the hour control signal are input, and the minute block signal or the hour block signal Signal as a timing signal, a minute advance circuit that outputs a minute advance signal that advances the count value of the auxiliary minute counter circuit when the minute block signal and the minute control signal are input; A data output circuit that receives a signal, an hour signal, a minute control signal, and an hour control signal, and outputs the hour signal or the minute signal as a data signal; and the data signal, the timing signal, and the clock signal that are input. Of the required numerical value and the hour signal of the required numerical value among the data signals are read by the timing signal, and a plurality of display clock parts for displaying the time by the minute signal and the hour signal are provided. And world clock.