JPS625677Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a digital electronic watch with an alarm used in automobiles and the like.

Conventionally, there are digital electronic watches equipped with this type of alarm function that, once the alarm is set, do not ring at the same time every day, but instead ring or do not ring depending on the day of the week. However, with such conventional electronic clocks, it is extremely inconvenient to not know whether the alarm is sounding or not, and adding a separate display function for this purpose would take up space and space. This was not desirable from the point of view of cost.

The present invention was developed in consideration of these points, and by effectively using the AM display and PM display segments in the digital display to indicate whether or not to disable the alarm, it takes up less space and reduces costs. The purpose of the present invention is to provide a digital electronic watch that makes it possible to reduce the

Embodiments of the present invention will be described in detail below with reference to the drawings.

The figure is a block diagram showing an embodiment of the digital electronic timepiece according to the present invention. In the figure, 1 is the water oscillator Q, inverter IN and capacitor
₂ is a frequency divider that divides the time reference signal input from oscillation circuit 1 into multiple stages and outputs a second signal and a fast forward signal, respectively; ₃ is a seconds counter, 4 is a clock counter, 5 is a clock hour counter, 6
7 is an alarm minute counter, 7 is an alarm hour counter, and 8 is a clock counter 4, 5 and an alarm counter 6, 7. The clock information is switched to display the time according to the on/off operation of a display changeover switch, which will be described later. A display selection circuit for displaying the alarm setting time; 9 a decoder for decoding the time display switched by the display selection circuit 8; and a decoder for decoding information on the alarm setting time display; 10 a 4-digit 7 segment
This is a driver that drives the digital display 11 consisting of SG ₁ to SG ₄ , and this driver 10 drives the digital display 11 by the output from the decoder 9.
minute, ten minute, hour, and ten o'clock segments
While driving SG ₁ to SG ₄ , the 7 segment SG ₄ of the 10 o'clock digit of the digital display 11 is driven by the output input to e and f of the 7 segment terminals of the 10 o'clock digit.
It is designed to drive "e" and "f". Reference numerals 12 and 13 indicate AM/clock and alarm time counters 5 and 7, into which time information is input.
These counters 12 and 13 are PM counters, and these counters 12 and 13 output a signal of "L" level when it is AM, and a signal of "H" level when it is PM. 1
4 is a matching circuit that compares the information of the clock counter and alarm counter based on the signals of the AM/PM counters 12 and 13 and outputs an "H" level signal when they match; 15 is a matching circuit 14;
This is an AND gate into which the output of the flip-flop and the output of a flip-flop (described later) are input, and this output is “H”.
The level signal turns on an alarm generator (not shown).

S ₁ is an externally operated switch that corrects the amount, and when turned on, this switch S ₁ sends a "L" level signal to the AND gate 1 to which the output of the AND gate 21 is input at one end via the inverter 16.
9 is input to the other end. And gate 19
The output of is inputted to the other end of an exclusive OR gate 25 which has the output of the seconds counter 3 inputted to one end thereof, and the output of this exclusive OR gate 25 is inputted to the minute counter 4 for the clock. _S2 is a time correction switch, and when turned on, this switch _S2 inputs a "L" level signal via an inverter 17 to one end of the AND gate 20, which receives the output of the AND gate 21, and the other end thereof. There is. The output of the AND gate 20 is input to the other end of an exclusive OR gate 26 which has one end inputted with the output of the clock minute counter 4, and the output of this exclusive OR gate 26 is inputted to the clock hour counter 5. There is. _S3 is a display changeover switch for switching between time display and alarm setting time display, and this switch _S3 selects time display when it is off, and selects alarm setting time display when it is on. That is, the display changeover switch _S3 inputs an "L" level signal to the display selection circuit 8 via the inverter 27 and the timer 28, and this display selection circuit 8 clocks when the "L" level signal is input. When an "H" level signal is input, the alarm counter is output as a display for a preset time in the timer 28. Further, the output of the timer 28 is connected to the inverters 18, 29 and the AND gate 2.
The output of the inverter 18 is input to the other end of the AND gate 21, which has one end inputted with the fast-forward signal output of the frequency divider 2, and the other end of the AND gate 22 Frequency divider 2
The fast forward signal output is input. The output of the AND gate 22 is connected to an inverter 17 at one end.
The output of is input to the other end of the AND gate 24. The output of the AND gate 23 is input to the alarm minute counter 6, and the output of the AND gate 24 is input to the alarm hour counter 7. S ₄ is the hour setting/alarm switch,
This switch _S4 inputs an "L" level signal to the mono multivibrator 31 in response to an on operation. The output of the mono-multivibrator 31 is input via an inverter 32 to the other end of a NAND gate 33, which has one end inputted with the output of the inverter 29, and is also inputted to the other end of an AND gate 30, which has one end inputted with the output of the timer 28. has been done. The output of the NAND gate 33 is input to the R (reset) terminal of the second counter 3 and the clock minute counter 4. 34 is the output of the AND gate 30 to the C _L (clock) terminal, and the R (reset)
It is a D-type flip-flop whose terminal receives the output of the differentiation circuit 35, and this output is input to the other end of the AND gate 15, which has the output of the matching circuit 14 input to one end, and also to the D (data input) terminal. Feedback is being provided. The output of the timer 28 is input to the differentiation circuit 35.

On the other hand, the output of the inverter 38 is input to the other end of the AND gate 36 which has one end inputted with the output of the AM/PM counter 12, and the output of this AND gate 36 is inputted to one end of the OR gate 39.
And, at the other end of the or gate 39, one end is connected to the other end.
The output of the AM/PM counter 13 is input, and the output of an AND gate 37 whose other end is input with the output of the timer 28 is input, and this OR gate 3
The output of 9 is input to one end of an OR gate 43 and is also input to one end of an OR gate 44 via an inverter 40 . Each of these or gates 43, 44
The output of the AND gate 42 is input to the other end, and the output of the timer 28 is input to one end of the AND gate 42.
The output of the flip-flop 34 is inputted to the other end via an inverter 41, respectively. The output of the OR gate 43 is input to the other end of an AND gate 46, which has one end inputted with the output of the OR gate 45, and the output of the OR gate 44 is input to the other end of an AND gate 47, which has one end inputted with the output of the OR gate 45. is input. Further, the output of the AND gate 46 is input to the 7-segment terminal e of the 10 o'clock digit of the driver 10, and the output of the AND gate 47 is input to the 7-segment terminal f of the 10 o'clock digit. Note that the inverter 38 is equipped with a timer 2.
The outputs of the inverter 17 and the timer 28 are input to the input terminal of the OR gate 45, respectively.

Next, the operation of the above embodiment will be explained. Here, it is assumed that the second counter 3 and the clock minute counter 4 are reset when an "L" level signal is input to the R terminal, and the flip-flop 34 is in a reset state. First, in the case of clock time display, when the display changeover switch S ₃ is turned off and the other minute and hour correction switches S ₁ and S ₂ and the hour setting/alarm switch S ₄ are also turned off as shown in the figure, the NAND gate 33 Inputs a “H” level signal when the display changeover switch S ₃ is turned off and a “L” level signal when the hour setting/alarm switch S ₄ turns off, and the output is “H”. It becomes a level signal,
The second counter 3 and the clock minute counter 4 are reset by the output of the NAND gate 33. When a time reference signal is input from the oscillation circuit 1 in this state, this time reference signal is multi-stage frequency-divided by the frequency divider 2, converted into a second signal, and inputted to the second counter 3. The signal is timed and inputted to a clock minute counter 4 through an exclusive OR gate 25, and the minute counter 4 inputs its output through an exclusive OR gate 26 to a clock hour counter 5. At this time, an "L" level signal is input to the display selection circuit 8 due to the turning off of the display changeover switch _S3 , and the display selection circuit 8 receives the clock information and time information of the hour counters 4 and 5. Decoder 9, driver 1
0 to the digital display 11, thereby causing the digital display 11 to display the usual "hours, minutes".
Perform display. In this case, the AND gate 21 receives the "H" level signal associated with the turning off of the display changeover switch _S3 , and outputs the fast-forward signal of the frequency divider 2 to the AND gates 19 and 20.

Next, when the minute correction switch _S1 is turned on in the above-mentioned "hour, minute" display, the AND gate 19 has one end set to "H" as the minute correction switch _S1 is turned on.
A level signal is input. Then, since the fast-forward signal is derived from the AND gate 21 at the other end of the AND gate 19, the fast-forward signal is sent to the exclusive OR gate 2 using the "H" level signal.
5 and input into the clock minute counter 4. Therefore, the minute counter 4 changes the clock information using the fast-forward signal, and while checking the time display on the digital display 11, the minutes can be corrected in fast forward mode while the minute correction switch _S1 is turned on. Furthermore, when the time correction switch _S2 is turned on, the "H" level signal associated with this turning on is input to one end of the AND gate 20, so that the AND gate 20
passes the fast-forward signal input from the AND gate 21, and this fast-forward signal is input to the clock hour counter 5 via the exclusive OR gate 26, so the time is adjusted in the same way as when the minute correction switch _S1 is set. Correction becomes possible. In such a time display, the AM/PM counter 12 to which the output of the clock hour counter 5 is input inputs a "L" level signal to the AND gate 36 during AM, and this signal is sent to the inverter via the OR gate 39. The "H" level signal inverted at 40 is input to the AND gate 47 via the OR gate 44, but the AND gate 47 receives the "L" level signal from the OR gate 45.
The gate is closed by the level signal, and the segment "f" in the 10 o'clock digit of the digital display 11 is not lit, and no AM display is performed. Also PM
The same applies to time.

On the other hand, when setting the hour, when the hour setting/alarm switch _S4 is turned on, the mono multivibrator 31 is triggered by the "L" level signal accompanying the turning on of the switch _S4 , and its output is A pulse signal of "L" level is generated and inputted to one end of the NAND gate 33 via the inverter 32.
Then, the "H" level signal associated with the turning off of the display changeover switch _S3 is input to the other end of the NAND gate 33, so the NAND gate 33 sends the "L" level output to the second counter 3 and the clock minute counter. 4 to reset them at the same time. Therefore, when the display changeover switch _S3 is in the time display mode and the hour setting/alarm switch _S4 is turned on, this switch _S4 becomes capable of setting the hour. At this time, an "H" level signal is input to one end of the AND gate 30 when the switch _S4 is turned on, while a "L" level signal is input to the other end when the display changeover switch _S3 is turned off. ” level signal is input, the output of the AND gate 30 is “L”
The flip-flop 34 maintains the reset state.

By the way, the alarm minute and hour counter 6,
Assuming that the alarm time is set in advance in 7, when the clock minute and hour counters 4 and 5 and the alarm minute and hour counters 6 and 7 match, the coincidence circuit 14 outputs an "H" level signal. is input to one end of the AND gate 15. Then, the output of the flip-flop 34, that is, the "H" level signal is input to the other end of the AND gate 15, and its output becomes an "H" level signal. As a result, an alarm generator (not shown) is turned on by the output of the AND gate 15 and generates an alarm sound.

Next, to disable the alarm in the clock circuit as described above, turn on the display changeover switch _S3 and turn on the hour setting/alarm switch _S4.
When turned on, a pulse obtained by differentiating the "H" level signal caused by turning on the display changeover switch S3 by the differentiating circuit ₃₅ is input to the R input of the flip-flop 34 as a reset signal. Retain its reset state. However, because the AND gate 30 receives the "H" level signal associated with the turning on of the display changeover switch _S3 and the hour setting/alarm switch _S4 , its output becomes a "H" level signal. , the "H" level output of the AND gate 30 is supplied to the C _L input of the flip-flop 34. At this time, the D input of the flip-flop 34 has an output of "H".
The flip-flop 34 reads the "H" level output of the AND gate 30, and generates an "H" level signal at the Q output and an "L" level signal at the output. Therefore, the AND gate 15 is inhibited by the "L" level signal of the output of the flip-flop 34, and is maintained in this state regardless of the output of the coincidence circuit 14. When the output of the flip-flop 34 becomes an "L" level signal, this signal is passed through an inverter 41 to an AND gate 4 to which the "H" level signal associated with the turning on of the display changeover switch _S3 is input.
2 is input to the other end. At this time, and gate 4
Since the gates 6 and 47 are opened by the "H" level signal associated with the turning on of the display changeover switch _S3 , the "H" level output of the AND gate 42 is connected to the OR gates 43, 44 and 47, respectively. It is input to the 10 o'clock segment terminals e and f of the driver 10 via AND gates 46 and 47. As a result, the 10 o'clock segments "e" and "f" of the digital display 11 are lit at the same time regardless of the output of the AM/PM counter 13, and the segments "e" and "f" are lit at the same time. You can know when alarms are prohibited. That is, when the hour setting/alarm switch S4 is turned on while the display changeover switch _S3 is displaying the alarm setting time, the switch _S4 can set the alarm prohibition state, and the alarm prohibition state can also be disabled _. Digital display 11
You can tell from the simultaneous lighting of the 10 o'clock segments "e" and "f". At this time, the NAND gate 33 is set to "L" as the display changeover switch _S3 is turned on.
Since the level signal is input, the hour setting/
The "H" level output is maintained regardless of the ON operation of the alarm switch _S4 .

In addition, when the alarm setting of the display changeover switch S ₃ is in time display mode, the hour setting/alarm switch S ₄
When the flip-flop 34 is turned on and then turned on again, the D input of the flip-flop 34 is at the "L" level, and the "H" level output from the AND gate 30 is supplied as the clock input to its C _L input as described above. , Q and output are inverted. Therefore, the output from the flip-flop 34 that has changed from the "L" level to the "H" level signal is input to the AND gate 15, the AND gate 15 changes from the alarm prohibition state to the alarm release state, and the digital display 11 also returns to its initial state. return. Therefore,
Alarm setting of display changeover switch _S3 During the display mode, each time the hour setting/alarm switch _S4 is turned on, alarm prohibition and alarm cancellation are alternately repeated, and in response to this operation, the digital display 11's 10 The display contents of the hour digit segments "e" and "f" can be changed. In addition, in the alarm setting display mode, the AM/PM counter 13 to which the output of the clock counter 7 is input inputs a "L" level signal to the AND gate 37 during AM, and this signal is passed through the OR gate 39. The “H” level signal inverted by the inverter 40 passes through the OR gate 44 and the AND gate 47 to the driver 1.
Since it is input to the 10 o'clock digit segment terminal f of 0,
The driver 10 selectively drives each segment SG ₁ to _{SG 4} of the digital display 11 based on the output of the decoder 9, and also drives the AND gate 47.
The "H" level signal causes the segment "f" of the 10 o'clock digit to be lit to display AM. Also
During PM, an "H" level signal output from the AM/PM counter 13 causes the AND gate 37 to send a "H" level signal to the 10 o'clock digit segment terminal e of the driver 10 via the OR gates 39, 43 and the AND gate 46. To input the information, the digital display 11 lights up the segment "e" of the 10 o'clock digit to display the PM in the same manner as described above.

In the above embodiment, the segments "e" and "f" of the 10 o'clock digit of the digital display used for AM and PM indications are lit at the same time, and depending on whether or not they are lit, an indication of prohibition or cancellation of the alarm is displayed. Although the present invention is not limited to this case, the present invention is not limited to this, and other than the segments "b" and "c" that display the number "1" in the 10 o'clock digit, It is also possible to selectively light up ``d'' to ``g'' or to light one of these segments to indicate whether the alarm is prohibited or canceled. In addition to the alarm switch that also serves as an hourly setting, we also configure a switch that has the function of disabling and canceling the alarm.
Of course, the circuit system can be changed to a logic circuit different from that of the above embodiment, or the timer 28 can be omitted.

As explained above, the present invention provides a digital electronic watch with an alarm equipped with a digital display, which is provided with a switch for setting the prohibition and cancellation of the alarm, and when the switch is set, the 10 o'clock digit of the digital display is We selected the morning segment and the afternoon segment from among the other segments excluding the segment that displays the number "1", and when alarm prohibition is set, both segments are lit at the same time, so this lighting display It is possible to know whether to inhibit or cancel an alarm from the above information, and this has the effect of reducing space and cost.

[Brief explanation of the drawing]

The figure is a block diagram showing an embodiment of the digital electronic timepiece according to the present invention. 1... Oscillation circuit, 2... Frequency divider, 3... Second counter, 4... Minute counter for clock, 5... Hour counter for clock, 6... Minute counter for alarm, 7... Hour counter for alarm. , 8...display selection circuit, 9...decoder, 10...driver,
11...Digital display, 12,13...AM/
PM counter, 14... Matching circuit, 15, 19~
24, 30, 36, 37, 42, 46, 47...
And gate, 16-18, 27, 29, 32,
38, 40, 41... Inverter, 25, 26...
...Exclusive or gate, 28...Timer, 31...Mono multivibrator, 33...
Nandgate, 34...Flipflop, 35
... Differential circuit, 39, 43, 44, 45 ... OR gate, S ₁ ... Minute correction switch, S ₂ ... Hour correction switch, S ₃ ... Display changeover switch, S ₄ ... For hour adjustment/alarm Switch.

Claims (1)

[Scope of utility model registration request] In a digital electronic clock with an alarm equipped with a digital display, there is a switch S4 that sets alarm prohibition and alarm enable, and a digital display 10.
Circuits 36, 37, 47 that light up and display one of the segments other than the segment that displays the number "1" in the hour digit as the AM segment, and the segment that displays the number "1" in the 10 o'clock digit of the digital display. and circuits 36, 37 for lighting and displaying one of the segments other than the morning segment as the afternoon segment;
46, and circuits 42, 46, and 47 for simultaneously lighting and displaying the morning segment and the afternoon segment when alarm prohibition is set by a switch.