JPH0633435Y2 - Digital clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a digital timepiece capable of time difference correction.

(Prior Art) In recent years, travel to the open sea has become frequent, but since there is a time difference between countries and regions, a digital timepiece having a function of correcting the time difference has been proposed.

This type of digital timepiece is additionally provided with a time difference correction switch, and the time difference of the displayed time is corrected to the up side or the down side by operating these switches.

(Problems to be solved by the invention) However, according to the digital timepiece described above, the time difference is corrected by the up-side or down-side correction switch. In addition, it is necessary to separately provide a dedicated time difference correction switch. Therefore, in the conventional digital timepiece, the structure is complicated and the appearance is deteriorated.

Then, this invention aims at solving the said subject by making an ordinary correction switch serve also as a time difference correction switch.

(Means for Solving the Problems) A digital timepiece according to the present invention comprises a reference signal generating circuit for generating various reference signals, a minute counter for counting minutes of the timepiece based on the reference signal, and a time counter for counting time. A counter section having a display section for displaying the time counted by the counter section, a reset switch, and a switch circuit having an up switch and a down switch for respectively correcting the display time up and down by an external operation, A display correction circuit for outputting a carry signal of the minute counter to the time counter, outputting a correction signal to the minute counter in place of the reference signal by the operation signal of the up and down switches, and correcting the display time; Outputs a reset signal that clears the second counter by operating the reset switch. In a digital timepiece having a reset circuit, a time difference correction circuit that outputs a time difference correction signal to the display correction circuit according to the operation signal of the up and down switches and a reference signal to correct the time digit of the display time, and the reset signal. And a mode switching circuit for selecting whether to output the operation signal to the time difference correction circuit or the display correction circuit based on the above.

(Operation) When the normal time adjustment is performed, the reset switch is turned on and then the correction switch is turned on within a predetermined time, so that the operation signal from the correction switch is input to the display correction circuit in the mode switching circuit to display the display. The correction circuit outputs a display correction signal to the display unit to correct the time.

In the case of time difference correction, by turning on the correction switch, the operation signal from the correction switch is input to the time difference correction circuit in the mode switching circuit, and in the time difference correction circuit, the display is performed based on the operation signal and the reference signal. The time digit corrected by the correction circuit and the time difference corrected is displayed on the display unit.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the digital timepiece 1 of this embodiment has a reference signal generating circuit 2 for generating various reference signals φ _{0 to} φ _4.
A counter section 4 for counting the minutes and hours of the time based on the reference signal; a display section 11 for displaying the time counted by the counter section 4; and a switch circuit for correcting the display of the display time by an external operation. 15, a display correction circuit 16 for correcting the display time at high speed when the operation signal output from the switch circuit 15 is output for a certain time or more, and a minute counter of the counter unit 4 by operating the reset switch of the switch circuit 15. A reset circuit 35 that outputs a reset signal that clears 8 and a time difference correction circuit 40 that outputs a time difference correction signal to the display correction circuit 16 based on the operation signal and the reference signal to perform time difference correction.
And a mode switching circuit 45 that selects whether to output the operation signal to the time difference correction circuit 40 or the display correction circuit 16 based on the reset signal.

The reference signal generating circuit 2 is composed of an oscillator 3, a frequency divider I, and a frequency divider II.
Outputs φ ₀ , φ _1, ... φ ₄ .

The counter unit 4 includes a second counter 5 and a one-minute counter 6.
Minute counter 8 consisting of 10-minute counter 7 and time counter 9
And the like, and counts seconds, minutes, and hours, respectively, based on the reference signal of 1 Hz. Further, at the time of time correction and time difference correction, in response to an output signal of a flip-flop 50 of a mode switching circuit 45 described later, up or down counting is performed to correct or correct the minute digit or the hour digit.

The display unit 11 includes a decoder 12, a display device 13 including a liquid crystal, etc.
And a driver 14 for driving the display 13 and the like, and displays the time based on the time counted by the counter unit 4.

The switch circuit 15 is a switch for advancing time.
S _u , a switch S _d for delaying time, and a reset switch S _r for zeroing, and the correction switches S _u , S _d output the operation signal U or D.

The display correction circuit 16 is composed of a minute digit input circuit 17 and a time digit input circuit 25. The minute digit input circuit 17 is
AND circuit 18, 19, 21, 22, OR circuit 20, knot circuit 23, 3
It is composed of a 0-base counter 24, and outputs a minute count signal by a carry signal of a second counter during normal time counting operation, and at the time of time adjustment, reference signals φ ₀ , φ ₁ and operation signal U.
The digit of the minute is corrected based on the operation signal D (down side) (up side). The time digit input circuit 25 is an AND circuit 26,2.
7, 29, OR circuits 28, 30, 32, and flip-flop 31, and outputs the hour count signal by the carry signal of the minute counter during the normal timekeeping operation. When the time difference correction signal Q ₂ and the time are adjusted, the time digit is changed by the carry signal from the minute counter 8 or the step signal when the count value of the 10-minute counter is 30 minutes or more in response to the reset signal described later. Make corrections.

The reset circuit 35 resets the frequency dividing circuit II, the second counter 5, and the n-ary counter 52 by operating the reset switch to set the mode of the second correction and correction switch to the normal time correction mode. In addition, input to the C input of the flip-flop 31 to sort 30 minutes, and if the minute digit is 30 minutes or more, 1 is set to the hour digit.
Step forward. After that, the minute counter 8 is cleared by the reset signal RE.

The time difference correction circuit 40 includes AND circuits 41 and 42 and a decade counter 43, and outputs the time difference correction signal to the time digit input circuit 25 of the display correction circuit 16 based on the reference signal φ ₂ and the operation signal U or D. To do.

The mode switching circuit 45 includes an OR circuit 46, 51, an AND circuit 47, 48, 49, 53, an n-ary counter 52, a flip-flop 50.
And a reset signal R from the reset circuit 35
The operation signals U and D can be output to the display correction circuit 16 for a certain period of time after the occurrence of, and the operation signals are normally output to the time difference correction circuit 40.

Next, the operation of the digital timepiece 1 having the above configuration will be described.

First, the case of time difference correction will be described.

In this case, by turning on the switch S _u on the up side or the switch S _d on the down side, a pulse for advancing the time digit of the display time at regular time intervals is generated to raise or lower the time digit. Then, the time difference is corrected.

For example, when the up-side switch _Su is turned on at time t ₁ in FIG. 2, the operation signal U is input from the AND circuit 42 to the time difference correction circuit 40 through the OR circuit 46 and the AND circuit 48 of the mode switching circuit 45. , The decade counter 43 is reset, and the decade counter 43 starts counting based on the reference signal φ ₂ . In the decade counter 43, a signal is output from the φ ₂ terminal every predetermined time,
The signal SH is input to the time counter 9 through the AND circuit 26 and the OR circuits 28 and 32, and the display section 11 is corrected to increase the hour digit by the number of generated pulses.

When the down side switch S _d is turned on, the flip-flop 50 of the mode switching circuit 45 is reset by the operation signal D, and an H level signal is output from the terminal to the u / d terminal of the counter section 4. Therefore, the time counter 9 performs time difference correction in which the time digit is reduced by the number of pulses generated from Q _{2 of the} decade counter 43. Off correction switch S _u or S _d after performing the desired time difference correction in this manner, to be operated with the modified switch over a certain time, decade counter 43 and gate 41 Q _n is holding the H level And close 26, AND gate 42,49,
Open 27 and perform normal timekeeping.

Next, a case of correcting the normal time will be described.

When the reset switch S _r is turned on at the time t ₂ in FIG. ₂ , the Q output of the flip-flop 36 of the reset circuit 35 becomes H level, and this signal R resets the n-ary counter 52 to make Q _n L level. And AND gate
53 and 47 are opened, φ ₂ is input, and is output to the clock input C of the counter. The AND gate 53 outputs the operation signals of the correction switches _Su and S _d via the AND gate 47 until Q _n becomes the H level. Output to the display correction circuit 16. Further, this signal R is input to the frequency divider circuit II and the reset input terminal of the second counter 5 to reset the second, and also to the clock input C of the flip-flop 31 of the time digit input circuit 25, and the minute counter 48. When is 30 minutes or more, the time counter 9 is advanced by one step. Further, the Q output RE of the flip-flop 37 resets the minute counter 8 to zero its count value.

Here, when the correction switch _Su or _Sd is operated, the operation signal is output to the minute digit input circuit 17 of the display correction circuit 16 via the AND gate 47 which is already open. The operation signal from the AND gate 47 is the n-ary counter 52.
Due to the reset, Q _n will not close the AND gate 47 becomes the H level while the modified switch S _u, the S _d are operated.

In response to the operation signal, the minute digit input circuit 17 releases the reset of the 30-ary counter 24 via the inverter 23, opens the AND gate 18, and sets the reference signal φ ₁ to the OR gate 20.
It is also input to the minute counter 8 via 30 and the 30 decimal counter 24. When 30 steps are advanced, the AND gates 18 and 22 are closed by the carry signal from Q, and the AND gate 1
9 is opened to input the reference signal φ _{0 to} the minute counter 8 at high speed. That is, the time adjustment is first performed at a low speed of φ ₁ , and after being corrected for 30 minutes, at a high speed of φ ₀ . The carry signal from the minute counter 8 is input to the hour digit input circuit 25.
Is input to the time counter 9 via the AND gate 27 which is opened by Q _{n of the} decade counter 43.

When the correction switch S _d is operated, the flip-flop is reset as described above, its Q output becomes H level, and the minute counter 8 and the time counter 9 of the counter unit 4 are down-counted.

Therefore, after pressing the reset switch, by operating the S _u or S _d modification switch within a predetermined time, in which it is normal time adjustment.

As described above, according to the present invention, if the correction switches S _u and S _d are first operated, the time digits are corrected to perform the time difference correction, and after the reset switch S _r is operated, the correction switches S _u and S _d are changed. The time can be adjusted normally by operating it.

(Effect of the Invention) As described above, according to the present invention, the time can be corrected normally by turning on the correction switch by pressing the reset switch and then turning on the correction switch. Therefore, even in the case of time difference correction, it can be used also as a normal correction switch, so that the number of switches does not increase, the timepiece can be simplified, and the appearance can be improved.

[Brief description of drawings]

1 and 2 relate to an embodiment of a digital timepiece of the invention, FIG. 1 is a circuit diagram thereof, and FIG. 2 is a schematic time chart thereof. 1 ... Digital clock, 2 ... Reference signal generation circuit 4 ... Counter section, 8 ... Minute counter 9 ... Time counter, 11 ... Display section 15 ... Switch circuit, 16 ... Display correction circuit 35 ... Reset circuit, 40 …… Time difference correction circuit 45 …… Mode switching circuit φ _{0 to} φ ₄ …… Reference signal, U, D …… Operation signal RE …… Reset signal

Claims (1)

[Scope of utility model registration request] 1. A counter signal generating circuit for generating various reference signals; a counter section having a minute counter for counting minutes of a clock based on the reference signal and a time counter for counting time; A display unit that displays the time counted by the unit; a switch circuit that includes a reset switch and that has an up switch and a down switch that up and down the display time by an external operation, respectively; A display correction circuit for outputting to a time counter and outputting a correction signal to the minute counter in place of the reference signal by the operation signal of the up and down switches to correct the display time; A reset circuit for outputting a reset signal for clearing the second counter; In a digital clock, a time difference correction circuit that outputs a time difference correction signal to the display correction circuit according to the operation signals of the up and down switches and a reference signal, and corrects a time digit of a display time; A digital timepiece comprising: a mode switching circuit for selecting whether to output an operation signal to a time difference correction circuit or a display correction circuit;