JPH04312Y2 - - Google Patents

Description

[Detailed description of the invention] (a) Industrial application field The present invention relates to a correction device for a digital watch, and in particular, it corrects the time one by one each time an external correction switch is turned on and off for a short time. This invention relates to an improvement in a correction device that adjusts the time forward when the switch is turned on for a certain period of time.

(b) Conventional technology As a conventional correction device of this type,
There was one shown in Publication No. 29243.

This correction device is configured to perform one count step correction and multiple count step correction depending on the length of operation time of one input key.

That is, by operating the input keys once at a time, the time can be corrected at once, and by continuing to operate the input keys for a certain period of time, it is possible to perform fast-forward correction.

(c) Problems to be solved by the invention In the above-mentioned conventional technology, fast-forward correction is often used to correct the time more quickly, but in this case, the device may advance too far or stop before the set time. I was often bored.

For example, when adjusting fast forward to adjust to 5 o'clock, if you confirm that the display has reached 5 o'clock and then turn off the switch, it will usually be past 5 o'clock.
When the time reaches 1 or 2 minutes, you have to make the correction again, and if you watch the display and operate by feeling while being careful not to advance too much, it usually shows 5 o'clock, such as 4:58 or 59. I often found myself at the previous time.

Generally, when adjusting the time, it is often the case that the time is set on the hour according to a time signal, etc., and it is often necessary to adjust the time quickly.

However, in the prior art, as described above, it is difficult to make corrections, and it takes a considerable amount of time to make corrections, especially if the process has progressed too far.

(d) Means for solving the problem This invention advances the time by continuously turning on the switch to set the hour on the hour, and when the time stops at 56 minutes before the hour, for example, the subsequent It is set so that addition corrections can be made by operating a switch, and when the timer stops at N+1:1 to 4 minutes after the hour, subtraction corrections can be made by operating a switch within a certain period of time.

The configuration of the present invention includes a reference signal generator, a timekeeping circuit that counts the current time using a signal from the reference signal generator, an external correction switch that supplies a single correction signal to the timekeeping circuit, and a correction external switch that supplies a single correction signal to the timekeeping circuit. a first counter that counts the signal from the reference signal generator only when the external switch for correction is operated; and after the first counter counts for a certain period of time, the external switch for correction ends the operation. a switching circuit that supplies a correction fast-forward signal from the reference signal generator to the timekeeping circuit in place of the correction single-shot signal until the correction is made; a time detection circuit that detects that the time measured by the up-down counter is within a certain period of time from a specific time; a count direction inversion circuit that detects that the signal supplied from the switching circuit to the clock circuit is switched from a fast-forward signal for correction to a single signal for correction, and inverts the counting direction of the up-down counter; The signal of the reference signal generator can be counted from the time when the counting direction of the up-down counter is switched by the inverting circuit,
The present invention is characterized by comprising a second counter that outputs a signal that returns the counting direction reversal circuit to its original state after a predetermined period of time has elapsed since the external correction switch was not operated.

(e) Examples Examples of the present invention will be described below based on the drawings.

FIG. 1 is a diagram showing the circuit configuration of a digital watch according to an embodiment of the present invention.

2 is an oscillator that generates a high frequency signal, and 4 is a frequency divider circuit that appropriately divides the high frequency signal and outputs a clock signal or the like.

8 is a time counting circuit having a minute counter 10 and an hour counter 12.

The minute counter 10 consists of an up-down counter, and counts the minute digits of the time by inputting a clock signal or the like inputted through the OR gate 6 to the clock input φ.

The hour counter 12 receives the output signal of the minute counter 10 and counts the hour digits of the time.

14 is a decoder driver that converts the count contents of the clock circuit 8 into a code signal, and 16 is a display section that digitally displays the time according to the signal from the decoder driver 14.

18 is an external switch for correction, 20 is a frequency dividing circuit 4
This counter inputs the clock signal φ ₁ from the external correction switch 18 to the clock input φ, and inputs the signal A ₁ from the external correction switch 18 inverted by the inverter 22 to the reset input R. 24 is counter 2
a flip-flop (hereinafter abbreviated as FF) which inputs the output signal _A2 of 0 to the clock input φ and inputs the output signal of the inverter 22 to the reset input R;
26 is an AND gate that inputs the signal A ₃ from the output Q of the FF 24 and the clock signal φ ₂ from the frequency dividing circuit 4, and 28 receives the signal A ₄ from the output of the FF 24 and the signal A ₁ from the external correction switch 18. The input AND gate 30 is this AND gate 26, 28
Input the output signal of and input the signal A ₇ to the OR gate 6
It is an OR gate that applies to .

32 is the clock input φ for the output signal _A3 of FF24.
FF, 34 inputs signal A ₈ from output Q of FF 32 and inputs signal A ₁₁ to U/D of minute counter 10.
It is an AND gate that applies to the input.

36 is a time detection circuit which inputs signals from the outputs Q ₀ to _{Q 6} of the minute counter 10 and applies a signal B ₇ to the AND gate 34 .

This time detection circuit 36 detects that the time counted by the minute counter 10 is within a certain period of time from a specific time.

This embodiment is configured to detect that 1 to 4 minutes have passed since the hour.

38 is a counter that inputs the clock signal φ ₁ to the clock input φ, and the signal A ₉ from the output of the FF 32 and the signal A ₁ from the external correction switch 18 are input.
The output signal of the OR gate 40 is input to the reset input R.

The output signal _A10 of this counter 30 is applied to the reset input R of the FF 32.

Next, the configuration of the time detection circuit 36 in the above configuration will be explained using FIG. 2.

As shown in FIG. 2, this time detection circuit 36 consists of a gate circuit.

AND gate 42 outputs the output Q ₂ of minute counter 10,
The signal from Q ₃ is inverted and input, and the signal B ₁ is output.

The AND gate 44 outputs the output Q ₀ of the minute counter 10,
Inverts the signals from Q ₁ and Q ₃ , inputs them, and outputs them.
Inputs the signal from Q ₂ as is and outputs signal B ₂ . OR gate 46 is the output of minute counter 10.
Input all signals from Q ₀ to Q ₃ and output signal B ₃ .

AND gate 48 inputs signal B ₁ and signal B ₃ ,
Output signal B ₄ .

The OR gate 50 receives the signals _B4 and _B2 and outputs the signal _B5 .

AND gate 52 outputs Q ₄ of minute counter 10.
~Q ₆ is inverted and input, and signal B ₆ is output.

AND gate 54 inputs these signals B ₆ and B ₅ ,
Outputs detection signal _B7 .

Next, the operation of this time detection circuit 36 will be explained first using the time charts shown in FIGS. 3 and 4. As shown in FIGS. 3A and 3B, the minute counter 10
In the output signal, outputs Q ₀ to _{Q 3} represent the 1-minute digit,
Outputs Q ₄ to Q ₆ represent 10 minute digits.

Therefore, the AND gates 42 and 44, the OR gate 46, the AND gate 48, and the OR gate 50, which input the outputs _Q0 to _Q3 , detect every 1 to 4 minutes, and input the outputs _Q4 to _Q6 . 52 is set to detect every 00 minutes.

That is, as shown in FIG.
becomes open when the outputs Q ₂ and Q ₃ reach the L level from 0 to 3 minutes, and the output signal B ₁ becomes the H level,
The OR gate 46 sets its output signal _B3 to the L level only at 0 minutes when all the outputs _Q0 to _Q3 are at the L level.

Therefore, the output signal B ₄ of the AND gate 48 to which the signals B ₁ and B ₃ are input becomes H level in 1 to 3 minutes.

Moreover, the AND gate 44 outputs Q ₀ , Q ₁ , Q ₃
When only the L level output Q ₂ becomes H level, it becomes open and its output signal B ₂ becomes H level.

Therefore, the output signal B5 of the OR gate 50 which inputs the signal _B4 which becomes H level from 1 to 3 minutes and _the signal _B2 which becomes H level only from this 4 minutes is output from every 1 to 4 minutes. becomes H level.

On the other hand, the AND gate 52 is opened only at 00 minutes when all the outputs Q ₄ to Q ₆ are at the L level, and the output signal B ₆ is set at the H level.

Therefore, the output signal _B7 of the AND gate 54 which inputs this signal _B6 and signal _B5 is 1 with 0 in the 10th minute digit.
It becomes H level only when the minute digit is from 1 to 4, that is, from 01 to 04 minutes of N o'clock.

In this way, the output signal _B7 of the time detection circuit 36 is set to be at the H level only during the period from 01 to 04 minutes past the hour.

Next, the operation of the circuit shown in FIG. 1 will be explained using time charts shown in FIGS. 5 and 6.

In the initial state, counters 20, 38 and
FFs 24 and 32 are all in a reset state.

Further, the clock circuit 8 usually counts the clock signal inputted via the OR gate 6, and the count contents are displayed on the display section 16 via the decoder driver 14.
is displayed as the time.

The minute counter 10 in this timekeeping circuit 8 is configured to count up when the signal A ₁₁ input to its U/D input is at the L level, and to count down when the signal A ₁₁ is at the H level. There is. Normally, the Q output of the FF 32 is at the L level, and the AND gate 34 is kept closed, so the signal _A11 is at the L level.

Therefore, the counter 10 receives the clock input φ
It is in the state of up-counting the signal input to the.

To make a single correction of the time, it is sufficient to turn on and off the external correction switch 18 in a short period of time. In response to this operation, a pulse is generated in the signal _A1 , and the AND gate, which is normally open, is activated. 28 and OR gates 30,6 to the clock input .phi. of the minute counter 10.

As a result, the minute counter 10 is corrected by up-counting its count contents.

As shown in FIG. 5, the external correction switch 18
When the counter 20 is turned on for a certain period of time or more, the output signal of the inverter 22 becomes L level, so that the counter 20 is reset and starts operating. The counter 20 outputs a pulse to its output signal _A2 after counting for a certain period of time.

The pulse generated in this signal A ₂ is applied to the clock input φ of the FF 24, and this FF 24 changes the output signal A ₃ to a high level in synchronization with the falling edge of this input pulse.
level, switch output signal _A4 to L level.
Therefore, the AND gate 26 instead of the AND gate 28 is opened, and the clock signal φ ₂ from the frequency dividing circuit 4 is generated as its output signal A ₅ . This signal A ₅ is generated via an OR gate 30 into a signal A ₇ which is further applied via an OR gate 6 to the minute counter 10 .

As a result, the minute counter 10 is subject to fast-forward correction.

This fast-forward correction continues as long as the external correction switch 18 is kept on, and stops when the external correction switch 18 is turned off. That is, when the external correction switch 18 is turned off, the output signal of the inverter 22 becomes H level.
The FF 24 is reset, and its output signal A ₃ becomes L level and signal A ₄ becomes H level.

Therefore, the AND gate 26 is closed,
The clock signal φ ₂ is not generated on the signals A ₅ and A ₇ and the fast forward correction of the minute counter 10 is also stopped.

In this way, when the external correction switch 18 is turned off during fast-forward correction, and the FF 24 is reset and the signal A ₃ becomes L level, the output signal A ₈ of the FF 32 is changed in synchronization with the fall of the signal A ₃ . is H
level, output signal _A9 switches to L level.
When this signal _A8 becomes H level, the AND gate 34 becomes open.

At this time, if you try to set the hour to the hour (for example, 5 o'clock) but the corrected time is actually 5:02, the time detection circuit 36 will set the hour to 1 to 2, as described above. It detects that 4 minutes have passed and sets its output signal _B7 to H level.

Therefore, the output signal _A11 of the AND gate 34 becomes H level when the signal _A8 becomes H level, causing the minute counter 10 to count down.

At this time, when the external correction switch 18 is operated twice, a signal is sent through the AND gate 28 and OR gates 30 and 6, which are already open.
The pulse generated at A ₁ is applied to the minute counter 10, and the count value is counted down until 5 o'clock.
You can go back to 00 minutes.

If the external correction switch 18 is operated twice, the time is corrected to 5:00, but at this time the time detection circuit 36 detects that the time is outside the range of 01 to 04 minutes and outputs Set signal _B7 to L level.
Therefore, the output signal _A11 of the AND gate 34 also becomes L level, and the minute counter 10 returns to the up-counting state again.

On the other hand, when the output signal _A9 of the FF 32 becomes L level, the reset state of the counter 38 is released and the counter 38 is activated.

As shown in FIG. 5, this counter 38 inputs the pulse generated in the signal _A1 every time the external correction switch 18 is operated to the reset input R via the OR gate 40, so that the signal _A9 is When it reaches the L level and a certain period of time has been counted since the last operation of the external correction switch 18, the count is increased and a pulse is generated in the output signal _A10 .

The FF32 is reset by the pulse generated in this signal _A10 , and its output signals _A8 and _A9 are returned to the original L,
They each switch to H level.

Therefore, the AND gate 34 is closed, the signal A ₁₁ does not go to H level except during correction, and the minute counter 10 counts up in response to the subsequent single operation of the external correction switch 18. Return to state.

In addition, if you try to set the time to 5 o'clock by fast forward correction but stop at 4:58, the output signal _B7 of the time detection circuit 36 will remain at the L level as shown in Fig. 6. , the output signal _A11 of the AND gate 34 never becomes H level.

Therefore, when the external correction switch 18 is operated once twice, the minute counter 10 increments the single correction signal and can make the correction to 5:00.

In this way, in this embodiment, when setting the hour using fast forward correction, even if the time is advanced too far and it is past the hour, the time can be set back within a certain period of time. In order to prevent this, the clock is configured so that the time is always advanced by a correction signal when corrections are made other than in this case.

(f) Effects of the invention According to the invention, when adjusting the time, especially when setting the time on the hour, the time can be quickly adjusted in accordance with the time signal.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the circuit configuration of a digital clock according to an embodiment of the present invention, FIG. 2 is a diagram showing the circuit configuration of the time detection circuit shown in FIG. 1, and FIGS. 3 to 6 are time charts. It is. 2... Oscillator, 4... Frequency dividing circuit, 8... Timing circuit, 10... Minute counter, 12... Hour counter,
18... External switch for correction, 20, 38... Counter, 24, 32... Flip-flop.

Claims (1)

[Claims for Utility Model Registration] A reference signal generator; a clock circuit that counts the current time using a signal from the reference signal generator; an external correction switch that supplies a single correction signal to the clock circuit; a first counter that counts the signal from the reference signal generator only when the external correction switch is operated; and a first counter that counts the signal from the reference signal generator only when the external correction switch is operated; a switching circuit that supplies a correction fast-forward signal from the reference signal generator to the timekeeping circuit in place of the correction single-shot signal until the end of the correction; a time detection circuit having a counter and detecting that the time measured by the up-down counter is within a certain period of time from a specific time; a count direction inversion circuit that detects that the signal supplied from the switching circuit to the timekeeping circuit is switched from a fast-forward correction signal to a single-shot correction signal and inverts the counting direction of the uptown counter; and the counting direction. The signal of the reference signal generator can be counted from the time when the counting direction of the up-down counter is switched by the inverting circuit, and the counting starts after a certain period of time has elapsed since the external correction switch was not operated. A correction device for a digital timepiece, comprising: a second counter that outputs a signal for returning a direction reversal circuit to its original state.