JPH041516Y2 - - Google Patents

Description

[Detailed description of the invention] (Field of industrial application) When resetting the seconds, this invention determines that the time is behind when the second digit is greater than a preset value, and changes the minute digit to 1 minute. This invention relates to the improvement of an electronic clock with an automatic delay correction function that adds up.

(Prior art) The above-mentioned electronic clock is, for example,
It is disclosed in Publication No. 141367. according to this,
If you operate the second reset in accordance with the time signal, etc., there is generally no need to add one minute to the minute digits for delays of up to 30 seconds, and the time can be corrected with a single operation.

(Problem to be solved by the invention) However, in the above conventional technology, even if the time is ahead by 30 seconds or more, 1 minute is added to the minute digit, and in order to correct this 1 minute advance, 59 minutes are added to the minute digit. It was necessary to perform addition, which made the correction operation more complicated.

(Means for Solving the Problems) In order to solve these problems, the present invention consists of a minute counter that measures minute digits as an up-down counter, and this up-down counter is normally configured with an up-down counter. It is characterized in that when the step signal is outputted, the counter is in a down-counting state for a certain period of time, and the down-counting is performed in response to an operation signal of a minute correction switch.

(Example) A preferred example of the present invention will be described below based on the drawings. FIG. 1 shows a block circuit of an embodiment to which the present invention is applied, and FIG. 2 is a time chart showing its operation.

The oscillator 2 and frequency divider circuit 4 constitute a reference signal generation circuit that generates a 1Hz reference signal, and this reference signal is sequentially counted by a second counter 6, a minute counter 8, and an hour counter 10 to generate a time signal. It is being formed. This time signal is then supplied to the time display section 12, and the time is displayed on the display section 12.

The lock switch 14 is connected to the counters 6, 8, 1.
The output A of the switch 14 is connected to the AND gate 2 along with the outputs of the second correction switch 16, minute correction switch 18, and hour correction switch 20.
2, 24, and 26. Furthermore, the output A of the lock switch 14 is supplied to switching circuits 28 and 30, which cause the minute counter 8 and the hour counter 10 to supply a carry signal from the lower counter in the non-correctable state, and to supply a carry signal from the lower counter in the correctable state. A carry signal is prohibited and a correction signal can be supplied to the minute counter 8 and hour counter 10. Therefore, the output C of the AND gate 24 is supplied to the switching circuit 28 via the gate 32, and the output of the AND gate 26 is supplied to the switching circuit 30, respectively.

On the other hand, the output B of the AND gate 22 is sent to the reset terminal R of the second counter 6 via the automatic delay correction circuit 34.
supplied to If the count value of the seconds counter 6 is a preset value, for example "30" or more, and the second correction switch 16 is operated, the automatic delay correction circuit 34 determines that the measured time is delayed and starts the minute counter. This circuit outputs a step signal for adding 1 minute to 8.

A shift register is constructed from FF36, 38, and 40, and as shown in Figure 2, output B is "H".
When the clock signal φ ₁ from the frequency dividing circuit 4 is supplied for the first time, the output E becomes "H" and accordingly, the output I of the AND gate 42 also becomes "H". Then, when the clock signal φ ₁ is supplied, the output F is inverted to "H" and the output G is inverted to "L", and accordingly, the output I becomes "L". Output K becomes "H". Then, when the next clock signal φ ₁ is supplied, the output H becomes "L" and the output K becomes "L". As a result, when output B becomes "H",
First a single pulse is output at output I, then output K
A single pulse will be output.

The decoder 46 detects that the count value of the second counter 6 is
The output D is set to "H" when the range is "30" to "59", and the output D is supplied to the AND gate 48 along with the output I. Therefore, when the second correction switch 16 is operated when the count value of the second counter 6 is between "30" and "59", a single pulse as a step signal is output to the output J of the AND gate 48, and this is output to the OR gate 32.
is supplied to the switching circuit 28 via. Therefore, one minute is added to the minute counter 8 by the step signal. The output K of the AND gate 44 is supplied to the reset terminal R of the second counter 6, and the count contents of the second counter 6 are then cleared by the single pulse output to the output K.

Further, in this embodiment, the minute counter 8 is constituted by an up-down counter, and when "H" is supplied to the count switching terminal U/D, it counts up, and when "L" is supplied, it counts down. It's becoming like that. And count switching terminal U/D
is supplied with an output O from which a count switching signal is output from the count switching circuit 50.

The count switching circuit 50 normally causes the up-down counter to count up, and when a step signal is output, causes it to count down for a certain period of time, and includes an FF 52, an OR gate 54,
It is composed of an inverter 56 and a counter 58. OR gate 5 is connected to the set terminal S of FF52.
The output M of the lock switch 14 is supplied to the OR gate 54, and the output A of the lock switch 14 is inverted and supplied to the OR gate 54. Therefore, in a normal state, the FF 52 is in a set state, and the output O is "H". Therefore, the minute counter 8 performs an up-count. On the other hand, when the state is changed to a state in which correction is possible, the output M becomes "L" and the setting is released. When a step signal is outputted to the output J, the output O of the FF 52 is inverted to "L" at the rising edge of the signal inverted by the inverter 56, and the minute counter 8 starts counting down. Note that the inverter 56 ensures that an increment signal is provided before the minute count 8 is switched to down-counting. and output O
When the counter 58 becomes "L", the reset state of the counter 58 is released, so it starts counting for a certain period of time, for example, 2 seconds, and when the count ends, a count end signal is supplied to the set terminal S of the FF 52 via the OR gate 54. Therefore, the output O of the FF 52 is inverted to "H" again, and the minute counter 8 performs up-counting.

The present embodiment is configured as described above, and the operation will be explained below.

The operation at time _t1 in FIG.
This shows the operation when the seconds correction switch 16 is operated when the counter value is between "0" and "29". Here, since the output D is "L", no single pulse is output to the output J, and only a single pulse is output to the output K. Therefore, no step signal is supplied to the minute counter 8, and only the count value of the second counter 6 is cleared. Therefore, the output O of the count switching circuit 50 is held at "H", and the minute counter 8 is controlled to perform up-counting.

The operation at time _t2 shows the operation when the second correction switch 16 is operated when the count value of the second counter 6 is between "30" and "59". In this case, since the output D is "H", the automatic delay correction circuit 34 determines that the time measurement is delayed and sequentially outputs single pulses to the outputs J and K. Therefore, a step signal is supplied to the minute counter 8, and the count value of the second counter 6 is also cleared. Also,
Since a negative single pulse, which is an inverted step signal, is output to the output N, the FF 52 is inverted at the rising edge of the pulse. Therefore, the output O changes from "H" to "L", and accordingly, the minute counter 8 is controlled to count down. Also, the output O
The counting operation of the counter 58 is started from when the value becomes "L", and a count end signal is outputted to the output P after 2 seconds have elapsed. With this, FF52
is set, and the output O becomes "L" again.
is inverted to "H", and as a result, the counter 8 is controlled to perform up-counting.

Therefore, if the count value of the second counter 6 is between "30" and "59" not due to a delay in timekeeping but due to an advance, the minute is corrected during the counting operation of the counter 58, for example at time _T3 . switch 1
8 will subtract 1 from the minute counter 8, thereby causing the automatic delay correction circuit 34
This allows you to cancel the unnecessary addition. Of course, if the cause is a delay in timing, there is no need to operate the minute correction switch 18 during the counting operation of the counter 58.

(Effect of the invention) As described above, according to this embodiment, the count value of the second counter 6 changes from "30" to "59" due to the progress of time measurement.
When the seconds are adjusted, the automatic delay correction circuit 34
If an increment signal is supplied to the minute counter 8, then the minute correction switch 18 is
The count value of the minute counter 8 can be subtracted by 1 by operating only once, thereby making it possible to very easily correct unnecessary carry, which was troublesome in the past.

Note that the switching time of the count switching signal output from the count switching circuit 50 may be other than 2 seconds, and the switching time of the count switching signal outputted from the count switching circuit 50 may be set to FF5 immediately after the minute correction switch 18 is operated.
It is also possible to implement a configuration in which 2 is set.

As explained above, according to the present invention, unnecessary carry corrections due to automatic delay correction, which conventionally caused a 59-minute increment and caused trouble, can be corrected with a very simple operation. be able to.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing a preferred embodiment of the present invention. FIG. 2 is a time chart showing the operation of FIG. 1. 2... Oscillator, 4... Frequency divider circuit, 6... Second counter, 8... Minute counter, 16... Second correction switch, 18... Minute correction switch, 34... Automatic delay correction circuit, 50... Count switching circuit.

Claims (1)

[Claims for Utility Model Registration] A reference signal generation circuit that generates a reference signal of a constant period; a second counter and counter that counts the reference signal to form a time signal; and a second counter that clears the count value of the second counter. a correction switch; a minute correction switch that corrects the value of the minute counter; and an automatic delay correction that provides an increment signal when the second correction switch is operated when the count value of the second counter is greater than or equal to a preset value. and a switching circuit that increments the minute counter in response to a carry signal from the second counter or the increment signal and operation of the minute correction switch. and a count switching circuit that outputs a count switching signal that causes the up-down counter to normally count up and to count down for a certain period of time when the step signal is output. Electronic clock with delay correction function.