JPH041515Y2 - - Google Patents

Description

[Detailed description of the invention] (a) Industrial application field The present invention relates to a correction device for a digital watch, and in particular, it corrects the time one by one each time an external correction switch is turned on and off for a short time. This invention relates to an improvement in a correction device that adjusts the time forward when the switch is turned on for a certain period of time.

(b) Prior art As a conventional correction device of this type,
There was one shown in Publication No. 29243. This correction device is configured to perform one count step correction and multiple count step correction depending on the length of operation time of one input key.

That is, by operating the input keys one by one, the time can be corrected at once, and by continuing to operate the input keys for a certain period of time, it is possible to perform fast-forward correction.

(c) Problems to be Solved by the Invention In the prior art described above, fast-forward correction is frequently used to correct the time more quickly, but in this case, the time may be set too far forward.

In particular, in order to quickly adjust the time, it is desirable to fast-forward to a time closer to the correct time, and as a result, the time has often been advanced too much.

In this case, the time has to be adjusted again, which ends up prolonging the adjustment time.

(d) Measures to solve the problem The present invention is configured so that if the switch is operated again immediately after fast-forward correction, the correction will be subtractive, and after a certain period of time, it will return to normal addition correction. a clock circuit that counts the current time using its output signal; an external correction switch that supplies a single signal for correction to the clock circuit; A first counter outputs a detection signal after a certain period of time, and a correction fast-forward signal from a reference signal generator is sent to the timer circuit instead of a single correction signal from the time the detection signal is generated until the correction external switch is turned off. A digital clock having a switching circuit for supplying the clock, the timekeeping circuit comprising an up-down counter, and a count direction reversing circuit for reversing the up-down counter to a down-counting state when the corrective fast-forward signal stops; a second counter that counts time in response to the down counter being reversed to the down count state, and returns the count direction reversal circuit to the up count state after a certain period of time has elapsed since the external correction switch was not operated; It is characterized by having the following.

(e) Examples Examples of the present invention will be described below based on the drawings. FIG. 1 is a diagram showing the circuit configuration of a digital watch according to an embodiment of the present invention.

2 is an oscillator that generates a high frequency signal, and 4 is a frequency divider circuit that appropriately divides the high frequency signal and outputs a clock signal or the like.

Reference numeral 8 denotes a clock circuit for counting the clock signal etc. inputted via the OR gate 6, and is composed of an up-down counter.

10 is a decoder driver that converts the count contents of the clock circuit 8 into a code signal, and 12 is a display unit that digitally displays the time in accordance with the signal from the decoder driver 10.

14 is an external switch for correction, 16 is a frequency dividing circuit 4
The clock signal φ ₁ from the clock input φ is inputted to the clock input φ, and the signal A ₁ from the external correction switch 14 is input to the clock input φ.
This counter inputs a signal inverted by an inverter 18 to a reset input R.

20 is a flip-flop (hereinafter abbreviated as "FF") which inputs the output signal _A2 of the counter 16 to the clock input φ and the output signal of the inverter 18 to the reset input R; 22 the output Q of the FF 20;
24 is an AND gate that inputs the signal A ₃ from the FF 20 and the signal φ ₂ from the frequency dividing circuit 4, and 24 is the signal A ₄ from the output of the FF 20 and the signal from the external correction switch 14.
A AND gate that inputs ₁ , 26 inputs the output signals of AND gates 22 and 24, and inputs the signal
This is an OR gate that applies _A7 to OR gate 6.
28 is an FF which inputs the output signal A ₃ of the FF 20 to the clock input φ and applies the signal A ₈ from its output Q to the U/D input of the up-down counter 8.

30 is a counter that inputs the clock signal φ ₁ to the clock input φ, and the signal A ₉ from the output of the FF 28 and the signal A ₁ from the external correction switch 14 are input.
The output signal _A10 of the OR gate 32 is input to the reset input R.

The output signal A11 of this counter ₃₀ is applied to the reset input R of the FF28.

The operation of the digital timepiece correcting device having the above configuration will be explained using the time charts shown in FIGS. 2 to 4.

In the initial state, counters 16, 30 and
All FFs 20 and 28 are in a reset state.

Further, the clock circuit 8 normally counts a 1 Hz clock signal inputted through the OR gate 6, and the count contents are displayed as the time on the display unit 12 via the decoder/driver 10.

This clock circuit 8 counts up when the signal A ₈ input to its U/D input is at L level,
Further, it is configured to count down when the signal _A8 is at H level.

Normally, FF28 is in the reset state, so the signal
_A8 is at the L level, and the timer circuit 8 is in a state of up-counting the signal input to the clock input φ.

Now, as shown in FIG. 2, if the external correction switch 14 is turned on and off in a short period of time, the signal A ₁
A pulse is generated according to that single operation.

The pulse generated in this signal _A1 is normally FF20
Since the output signal A ₄ of is at H level, it is generated as the output signal A ₆ of the AND gate 24 which is in an open state, and further generated as the signal A ₇ via the OR gate 26 .

This signal _A7 is applied to the clock circuit 8 via the OR gate 6, and the count contents are up-counted and corrected.

Note that the counter 16 is connected to an external correction switch 14.
When the inverter 18 is turned on, the output signal of the inverter 18 becomes L level, so the reset is released and the inverter starts operating.However, since the time that the inverter is turned on is short, it returns to the reset state again before the count-up occurs. It does not output pulses.

Therefore, the output states of the FFs 20, 28, etc. do not change. Next, as shown in FIG. 3, when the external correction switch 14 is turned on for a certain period of time or longer, the counter 16 is reset and activated while it is turned on.

After counting for a certain period of time, this counter 16 outputs a pulse to its output signal _A2 .

The pulse generated in this signal A ₂ is applied to the clock input φ of the FF 20, and this FF 20 changes the output signal A ₃ to a high level in synchronization with the falling edge of this input pulse.
level, switch output signal _A4 to L level.
Therefore, the AND gate 22 instead of the AND gate 24 is opened, and the clock signal φ ₂ from the frequency dividing circuit 4 is generated as its output signal A ₅ .

This signal _A5 is passed through the OR gate 26 to the signal A5.
The signal is generated at A ₇ and is further applied to the clock circuit 8 via the OR gate 6 .

As a result, the clock circuit 8 is corrected for fast forwarding. This fast-forward correction continues as long as the external correction switch 14 is kept on, and stops when the external correction switch 14 is turned off. That is, when the external correction switch 14 is turned off, the output signal of the inverter 18 becomes H level, the FF 20 is reset, and the output signal
_A3 becomes L level and signal _A4 becomes H level. Therefore, the AND gate 22 is closed and the signal
The clock signal φ ₂ is not generated at A ₅ and A ₇ , and the fast-forward correction of the clock circuit 8 is also stopped.

In this way, when the external correction switch 14 is turned off during fast-forward correction, and the FF 20 is reset and the signal A ₃ becomes L level, the output signal A ₈ of the FF 28 is changed in synchronization with the fall of the signal A ₃ . is H
level, output signal _A9 switches to L level.
When this signal _A8 becomes H level, the timer circuit 8 enters a state in which it counts down the input signal. At this time, when the external correction switch 14 is operated once to generate a pulse in the signal _A1 , this pulse is generated in the output signal _A6 of the AND gate 24, which is already in the open state, and the OR gates 26, 6 is applied to the clock input φ of the timer circuit 8 via the clock input φ. At this time, the clock circuit 8 counts down the signal input to the clock input φ and corrects the count contents.

On the other hand, when the output signal A ₉ of the FF 28 becomes L level, the output signal A ₁₀ of the OR gate 32 also becomes L level, and the counter 30 is activated.

As shown in FIG. 3, this counter 30 inputs the pulse generated in the signal _A1 through the OR gate 32 to the reset input R each time the external correction switch 14 is operated. When _A9 becomes L level and a certain period of time is counted from the last operation of the external correction switch 14, the count is increased and a pulse is generated in the output signal _A11 .

The FF 28 is reset by the pulse generated in the signal A ₁₁ , and its output signals A ₈ and A ₉ are returned to the original L,
They each switch to H level.

As a result, the clock circuit 8 returns to its original up-counting state.

If the external correction switch 14 is operated immediately after the fast-forward correction is made in this way, the clock circuit 8 can be caused to count down.

Furthermore, as shown in FIG. 4, if the external correction switch 14 is not operated until the counter 30 is activated and counts up after the fast forward correction is made in the same manner as the above operation, the pulse generated in the signal A ₁₁ will
The FF 28 is reset and the timer circuit 8 returns to the up-count state again.

Thereafter, by operating the external correction switch 14 again, the count contents of the timer circuit 8 can be corrected in one shot or fast-forwarded in the same manner as described above.

(f) Effects of the invention According to the invention, even if the time is set too far by mistake when making fast-forward adjustments, the time can be corrected by subtraction in a single operation by operating the switch immediately afterward, making it easy and quick. can be corrected at the correct time.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the circuit configuration of a digital clock according to an embodiment of the present invention, and FIGS. 2 to 4 are time charts. 2... Oscillator, 4... Frequency dividing circuit, 8... Timing circuit, 14... External switch for correction, 16, 30...
...Counter, 20, 28...Flip-flop,
22, 24...and gate, 26...or gate.

Claims (1)

[Claims for Utility Model Registration] A reference signal generator; a timekeeping circuit that counts the current time using a signal from the reference signal generator; an external correction switch that supplies a single correction signal to the timekeeping circuit; a first counter that counts the operation time as the external correction switch is operated and outputs a detection signal after a certain period of time; a switching circuit that supplies a correction fast-forward signal from the reference signal generator to the timekeeping circuit in place of the correction single-shot signal, wherein the timekeeping circuit is configured with an up-down counter; a count direction reversal circuit that inverts the up-down counter to a down-counting state when the signal stops; and a count direction reversing circuit that counts time when the up-down counter is inverted to a down-counting state, and controls the operation of the external correction switch. A correction device for a digital timepiece, comprising: a second counter that is returned to an up-counting state by the counting direction reversing circuit after a certain period of time has elapsed since the counting direction has stopped.