JPH0616360Y2 - Digital clock correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a correction circuit for a digital timepiece, and in particular, resetting the time by operating any of a plurality of correction switches during a specific time zone. Regarding what you can do.

(Prior Art) Conventional digital timepieces are generally provided with a switch for correcting the hour and minute digits and a reset switch for resetting including the seconds. By operating each switch, each digit is adjusted. Had been fixed.

(Problems to be solved by the invention) Generally, when the time is set, it is often set to the hourly time signal.

In this case, it is best to operate the reset switch, but if you operate other switches, not only will it not be possible to set the time to the hour on the hour, but you will also need to perform the operation to restore the changed digit. Become.

Therefore, in a timepiece provided with a plurality of switches as described above, it is troublesome that the switches must be carefully checked before they are operated.

An object of the present invention is to make it possible to reset the time no matter which switch is operated only in a specific time zone so that the time can be adjusted on the hour, and to easily and reliably perform the switch operation when adjusting the hour on the hour. .

(Means for Solving the Problems) A correction circuit for a digital timepiece according to the present invention comprises a clock signal generating circuit, a minute counter, an hour counter, a display circuit for displaying the time, and a switch group for outputting an operation signal. In a correction circuit having a display correction circuit that corrects the display by correcting the hour and minute counters according to the operation signal, a minute digit that detects a specific time zone from the count value of the minute counter and outputs a detection signal. A detection circuit, a reset control circuit that blocks the output of the detection signal in response to the operation signal, and a reset signal is applied to the minute counter in response to any operation signal from the switch group when the detection signal is generated and cleared. A reset circuit that applies a control signal to the display correction circuit to advance the count of the hour counter during carry, and an operation signal when the detection signal is not generated A circuit and an output selection circuit to be supplied to the display correction circuit.

(Operation) In the present invention, the operation signals from all the switches are supplied to the reset circuit through the output selection circuit only when the detection signal is output from the minute digit detection circuit.

The detection signal is output only when the minute digit detection circuit detects a specific time zone, for example, a time zone of 59 minutes to less than 01 minutes, and the switch is not operated at this time.

When the switch is operated, the reset control circuit blocks the output of the detection signal in response to the operation signal.

Therefore, if the time being corrected enters a specific time zone while the minute digit is being corrected, the operation signal will not be supplied to the reset circuit via the output selection circuit, and normal correction should be continued. You can

When an operation signal is supplied to the reset circuit when such a detection signal is generated, the minute counter is cleared.

If a carry is required at this time, that is, if the display at 11:59 is corrected to 12:00, the minute counter is cleared and the hour counter is incremented.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a correction circuit for a digital timepiece according to an embodiment of the present invention.

Reference numeral 2 denotes a clock signal generation circuit, which includes an oscillator 4 and first and second frequency dividers 6 that sequentially divide a high frequency signal output from the oscillator 4.
8 and a second counter 10 that counts the reference signal output from the second frequency divider 8 and outputs a time signal in which a pulse is generated once per minute.

Reference numeral 12 denotes a minute counter, and in the present embodiment, a 1-minute counter 14 for inputting a clock signal through a display correction circuit described later to count the 1-minute digit of the time and a carry signal output from the 1-minute counter 14 are input. 10 to count the 10th minute of the time
It is composed of a minute counter 16.

Reference numeral 18 is a time counter that counts the hour digits of time, and is a 10-minute counter 1 that is input via a display correction circuit described later.
The carry signal is counted from 6.

A display circuit 20 includes a decoder 22 for inputting the information signal indicating each time from the 1-minute counter 14, the 10-minute counter 16, and the hour counter 18 to convert it into a code signal, and a display drive by inputting the code signal. It is composed of a driver 24 that outputs a signal and a display 26 that inputs the display drive signal and digitally displays the time.

28-32 are an hour correction switch, a minute correction switch and a reset switch, respectively.

Reference numeral 34 is a display correction circuit, which is composed of a minute digit input circuit 36 and an hour digit input circuit 38 for applying counting signals to the minute counter 12 and the hour counter 18, respectively.

The minute digit input circuit 36 inputs an operation signal from the minute correction switch 30 to one input end via an output selection circuit described later and an AND gate 40 which inputs the clock signal ₁ to the other input end, and also outputs the same. An AND gate 42 for inverting the operation signal via the selection circuit and inputting the inverted signal to one input end and inputting a carry signal from the second counter 10 to the other input end, and output signals of these AND gates 40, 42 The OR gate 44 inputs and outputs a signal to the 1-minute counter 14.

Further, the hour digit input circuit 38 inputs an operation signal from the hour correction switch 28 to one input end via the output selection circuit and inputs the clock signal ₁ to the other input end.
Similarly, an AND gate 48 that inverts the operation signal via the output selection circuit and inputs the inverted signal to one input terminal and the carry signal from the 10-minute counter 16 to the other input terminal, and the output Q of the 10-minute counter 16 AND gate 50 for inputting signals from ₀ and Q ₁ , OR gate 52 for inputting its output signal and the signal from output Q ₂ of 10-minute counter 16, and its output signal for inputting to data input D will be described later. A flip-flop (hereinafter abbreviated as "FF") 54 for inputting a signal SR from a reset circuit to a clock input C, a signal from its output Q and a signal from AND gates 46 and 48 are input and applied to an hour counter 18. OR gate 56
It consists of and.

The AND gate 50, the OR gate 52 and the FF 54 constitute a distribution circuit for advancing the hour counter 18 by one when the 10-minute digit of the time when resetting is 30 to 50.

Reference numeral 58 denotes a minute digit detection circuit, which inputs the signals from the outputs Q ₀ and Q _{2 of the} 10 minute counter 16 so that the 10 minute digit of the time is 50.
AND gate 60 that outputs an H level signal when
And an AND gate 62 which inputs signals from the outputs Q ₀ and Q ₃ of the 1-minute counter 14 and outputs an H-level signal when the 1-minute digit of the time is 9, and output signals of the AND gates 60 and 62 AND gate 64 for inputting the output signal, an AND gate 66 for inputting the output signal and a signal from a reset control circuit described later, an output signal for the clock input C, and a detection signal for outputting the detection signal. To the data input D, and the output signal of the AND gate 60 is inverted and input to one input terminal, and the signal from the output Q ₀ of the 1-minute counter 14 is input to the other input terminal to calculate the time component. An AND gate 70 that outputs an H-level signal when the digit is 01, and an output signal that outputs the output signal and a signal from the reset control circuit and outputs the signal to the reset input R of the FF 68 It is composed of a board 72.

Reference numeral 74 is a reset control circuit, which outputs a detection signal and a timer circuit 76 for preventing the detection signal from being output from the minute digit detection circuit 58 for a fixed time when the hour correction switch 28 or the minute correction switch 30 is operated. The reset operation detection circuit 78 stops the output of the detection signal when the hour correction switch 28 or the minute correction switch 30 is operated.

The timer circuit 76 inputs an operation signal from the hour correction switch 28 and the minute correction switch 30.
An AND gate 82 for inputting a clock signal ₀ and inverting a signal from an output Qn of an n-ary counter, which will be described later, and an output signal of the AND gate 82 and an output signal of the OR gate 80 to a clock input C and a reset input R, respectively. The n-ary counter 88 applies a carry signal from the input Qn to the AND gate 66 in the minute digit detection circuit 58.

Further, the reset operation detecting circuit 78 inputs the detection signal to the reset input R, inputs it to the data input D via the inverter 90, and further inputs the signal SR from the reset circuit, which will be described later, to the clock input C, and its FF92. The signal from the output Q is input and the signal _A from the reset circuit is input to input the signal _A from the OR digit 72 in the minute digit detection circuit 58.
And AND gate 96 for applying a signal to.

Reference numeral 98 denotes a reset circuit, which is a time correction switch 28 and a minute correction switch 3 output via an output selection circuit described later.
OR gate 100 for inputting the operation signal from 0 and the operation signal from reset switch 32, and the signal output by OR gate 100
FF 102 which inputs _A to the clock input C and the signal from its output to the data input D, the signal from its output Q and the clock signal ₃ from the first frequency divider 6 to the data input D and the clock input, respectively. FF1 for inputting to C and further applying a signal from output Q to 1-minute counter 14, 10-minute counter 16 and each reset input R of FF102
04, and is composed.

An output selection circuit 106 inputs AND gates 108, 110 for inputting the operation signal from the time correction switch 28 to each one input terminal and for inputting the detection signal and its inverted signal to the other input terminals. It comprises AND gates 112 and 114 for inputting the operation signal from the correction switch 30 to each one input terminal and for inputting the detection signal and its inverted signal to the other input terminals respectively.

Next, the operation of the correction circuit having the above configuration will be described with reference to FIGS.
This will be described using the time chart shown in the figure. First,
The clock signal output from the second counter 10 is applied to the one-minute counter 14 through the normally-open AND gate 42 and the OR gate 44 to be counted.

The carry signal output by the 1-minute counter 14 every 10 minutes is applied to the 10-minute counter 16.

The carry signal output from the 10-minute counter 16 every 60 minutes is applied to the hour counter 18 via the normally-open AND gate 48 and the OR gate 56, and is counted here.

Now, when the minute digit of the time becomes 59 minutes, as shown in FIG. 2, the outputs Q ₀ and Q ₂ of the 10-minute counter 16 and the output Q ₃ of the 1-minute counter 12 are already at the H level at this time. Therefore, the output Q ₀ of the 1-minute counter 12 becomes H level.

Therefore, the output signals of the AND gates 60 and 62 for inputting the signals from these outputs both become H level, and the output signal of the AND gate 64 for inputting this output signal also becomes H level.

Here, the signal from the output Qn of the n-ary counter 88 is normally H
Since it is a level, the AND gate 66 for inputting this is in an open state.

Therefore, the H level signal from the AND gate 64 is generated at the output of the AND gate 66, and the FF 68 sets its output to the L level in synchronization with its rising.

In this embodiment, as described above, when the detection signal from the output of the FF 68 is at the L level, the generation state occurs,
When the level is reached, it is in a non-occurrence state. When the detection signal is generated in this manner, the AND gate 108 for inputting the detection signal,
112 becomes a closed state, and instead of this, AND gate 1
10, 114 are opened.

Here, the hour correction switch 28 or the minute correction switch 3
When any one of 0 is operated, the operation signal is applied to the OR gate 100 via the AND gate 110 or 114, and the output signal _A is generated.

In addition, in this embodiment, the reset switch 32 is provided, and when the reset switch 32 is operated, the operation signal is generated in the output signal _{A of the} OR gate 100 regardless of whether the detection signal is generated or not.

Therefore, when the reset switch 32 is operated, the reset switch 32 is always in the same state as when the hour correction switch 28 or the minute correction switch 30 is operated when the detection signal is generated. Need not be provided.

The FF 102 sets the signal SR from its output Q to H level in synchronization with the rising edge of the operation signal generated in the signal _A.

When the signal SR goes high, the second frequency divider 8 and the second counter 10 are reset at the same time.

Further, the outputs Q _{0 to} Q ₂ of the 10-minute counter 16 at this time
In this state, the H level signal is applied to the data input D of the FF 54, and therefore the FF 54 outputs the H level signal from its output Q in synchronization with the rising of the signal SR.

When this signal is input through the OR gate 56, the counter 18 advances the count by one step.

When the signal SR goes high, the FF 104 synchronizes with the clock signal ₃ and puts the signal from its output Q high.

Then, the 1-minute counter 14 and the 10-minute counter 16 are reset by this signal.

At this time, the signal from the output Q of the FF 104 is F
Since it is applied to the reset input R of the F102 and resets it, pulses are sequentially generated at the outputs Q of the FFs 102 and 104, and after operating the distribution circuit including the FF54, the minute counter is activated. Resetting twelve.

On the other hand, when a pulse is generated in the signal SR from the FF 102 as described above, the FF 92 to which the H level signal is applied to the data input D only when the detection signal is generated is output from the output Q of the FF 92 in synchronization with the rising of the signal SR. Set the signal to H level.

This signal is applied to one input of the AND gate 96 to open it.

An inverter 94 is provided at the other input terminal of the AND gate 96.
The signal _A is applied via the signal _A. Therefore, when the switch operation is completed and the signal _A becomes L level, the output signal of the AND gate 96 becomes H level.

This signal is applied to the reset input R of the FF 68 via the OR gate 72 to reset it. As a result, the detection signal output from the FF 68 becomes H level, and the non-generation state is set.

Further, if the switch operation is not performed when the detection signal that the minute digit of the time reaches 59 minutes as described above is generated,
As shown in FIG. 3, when the minute digit of the time reaches 01 minute, the detection signal is not generated. That is, the minute digit of the time is 00
At the minute, the outputs Q _{0 to} Q _{3 of the} 1-minute counter 14 and the 10-minute counter 16 become L level.

Therefore, the AND gates 60 and 62 are closed, and the AND gate 64 is also closed.

At this time, the AND gate 70 for inverting and inputting the output signal of the AND gate 60 is opened, and when the minute digit of the time becomes 01 minute, the H level signal from the output Q ₀ of the 1-minute counter 14 outputs the output. Occurs in. The output signal of the AND gate 70 at the H level is fed to the FF via the OR gate 72.
Applied to 68 and resetting it.

As a result, the time digit of the detection signal is generated only from 59 minutes to 01 minutes.

Further, if the hour correction switch 28 or the minute correction switch 30 is operated when the detection signal is not generated,
As shown in the figure, normal time adjustment can be performed.

That is, when the minute correction switch 30 is turned on, the operation signal is generated at the output of the AND gate 112 which is opened when the detection signal is not generated, and is applied to the AND gate 40 to open it.

Therefore, the clock signal ₁ is generated at the output of the AND gate 40 and is applied to the 1-minute counter 14 via the OR gate 44 to fast-forward and correct it.

If the minute digit of the displayed time becomes 59 minutes during such correction,
As described above, the 1-minute counter 14 and the 10-minute counter 16
The AND gates 60 and 62 for inputting the signal from the output and the AND gate 64 for inputting the output are opened.

If the AND gate 66 is in the open state, the detection signal is output from the FF 68 as described above. At this time, the operation signal is applied to the reset input R of the n-ary counter 88 via the OR gate 80. Since it is in the reset state, its output Qn is at the L level, which keeps the AND gate 66 closed.

Therefore, the FF 68 does not switch its output,
No detection signal is generated.

When the switch operation is completed, the n-ary counter 88 counts for a certain period of time by the clock signal ₀ from the AND gate 82, sets the output Qn to the H level, and stops in that state.

As a result, for example, even if the minute digit of the time is corrected to 59 minutes, the detection signal is not generated, so that when the time is corrected to 59 minutes, the time is not reset to 00 minutes.

(Effects of the Invention) According to the present invention, in the time zone when the hour is most often adjusted to the hour, no matter which switch is operated, the time can be reset and adjusted to the hour. It can be corrected without fail.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a correction circuit of a digital timepiece according to an embodiment of the present invention, and FIGS. 2 to 4 are time charts of the signals shown in FIG. 2 ... Time signal generation circuit, 12 ... minute counter, 18 ... hour counter, 20 ... display circuit, 28 ... hour correction switch, 30 ... minute correction switch, 32 ... reset switch, 34 ... display Correction circuit, 58 ... Minute digit detection circuit, 74 ... Reset control circuit, 98 ... Reset circuit, 106 ... Output selection circuit.

Claims (1)

[Scope of utility model registration request] 1. A time signal generating circuit for generating a time signal, a minute counter for counting the minute digits of the time by the time signal, and an hour counter for counting the hour digits of the time by a carry signal from the minute counter. , A display circuit for displaying the time counted by the hour counter and the minute counter, a switch group for outputting an operation signal by an external operation, and correcting the counts of the hour counter and the minute counter according to the operation signal. A display correction circuit for correcting the display of a display circuit, and a correction circuit for a digital timepiece having: a minute digit detection circuit for detecting a specific time zone based on the count value of the minute counter and outputting a detection signal; According to the reset control circuit for blocking the output of the detection signal, and any operation signal from the switch group when the detection signal is generated. In response, a reset signal is applied to the minute counter to clear it, and a control signal is applied to the display correction circuit to advance the count of the hour counter during carry, and a reset circuit when the detection signal is generated. A correction circuit for a digital timepiece, comprising: an output selection circuit which supplies an operation signal to the reset circuit and supplies the operation signal to the display correction circuit when the detection signal is not generated.