JPH0616361Y2 - Digital clock correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a correction circuit for a digital timepiece, and in particular, when the switch is operated for the first time, the time can be reset by operating any correction switch. Regarding what you can do.

(Prior Art) Generally, a conventional digital timepiece is provided with a switch for correcting the hour digit and the minute digit, a reset switch for performing a reset including the second, and the like. Had been fixed.

(Problems to be solved by the invention) Generally, when the time is set, it is often set to the hourly time signal. In this case, it is best to operate the reset switch, but if you operate other switches, not only can you not set the time on the hour, but you also need to return the changed digit to its original position. Become.

Therefore, in a timepiece provided with a plurality of switches in this way, it is troublesome to check the switches carefully before operating them.

An object of the present invention is to make it possible to reset the time and adjust to the hour on the hour no matter which switch is operated only for the first time operation, so that the switch operation at the time of hour can be easily and reliably performed. .

(Means for Solving the Problems) A correction circuit for a digital timepiece according to the present invention includes a clock signal generating circuit, a minute counter, a display circuit for displaying time, a switch group for outputting an operation signal, and an operation signal for the operation signal. In accordance with a correction circuit having a display correction circuit for correcting the display by correcting the hour and minute counters accordingly, a reset signal is applied to the minute counter in response to any operation signal from the switch group and the display is cleared. Outputs a reset circuit that applies a control signal to the correction circuit to advance the count of the hour counter when carrying, and a control signal that blocks the generation of the reset signal for a certain period of time in response to the stoppage of the operation signal when the reset signal is generated. Reset control circuit and an output selection circuit that supplies an operation signal to the display correction circuit when a control signal is generated and an operation signal to the reset circuit when a control signal is not generated. It consists of a road and a road.

(Operation) In the present invention, the operation signals from all the switches are normally applied to the reset circuit via the output selection circuit to output the reset signal, whereby the minute counter is cleared.
If a carry is required at this time, that is, if the display at 11:30 is corrected to 12:00, the minute counter is cleared and the hour counter is incremented.

When the generation of the operation signal is stopped while the reset signal is being generated, the reset control circuit outputs the control signal for a certain period of time in response to this. The output selection circuit
In response to this control signal, the operation signal from the switch is supplied to the display correction circuit. Therefore, when this control signal is generated, each digit of the time can be arbitrarily corrected by operating the switch.

Therefore, in the correction circuit of the present invention, when the switch is operated for the first time, any switch can be operated to set the hour on the hour, and if the switch is operated again within a certain time after the operation of the switch, the digit corresponding to this switch is changed. Can be modified arbitrarily.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a correction circuit for a digital timepiece according to an embodiment of the present invention.

Reference numeral 2 denotes a clock signal generation circuit, which includes an oscillator 4 and first and second frequency dividers 6 that sequentially divide a high frequency signal output from the oscillator 4.
8 and a second counter 10 that counts the reference signal output from the second frequency divider 8 and outputs a time signal in which a pulse is generated once per minute.

Reference numeral 12 denotes a minute counter, and in the present embodiment, a 1-minute counter 14 for inputting a clock signal through a display correction circuit described later to count the 1-minute digit of the time and a carry signal output from the 1-minute counter 14 are input. 10 to count the 10th minute of the time
It is composed of a minute counter 16.

Reference numeral 18 is a time counter that counts the hour digits of time, and is a 10-minute counter 1 that is input via a display correction circuit described later.
The carry signal from 6 is counted.

A display circuit 20 includes a decoder 22 for inputting the information signal indicating each time from the 1-minute counter 14, the 10-minute counter 16, and the hour counter 18 to convert it into a code signal, and a display drive by inputting the code signal. It is composed of a driver 24 that outputs a signal and a display 26 that inputs the display drive signal and digitally displays the time.

28 and 30 are an hour correction switch and a minute correction switch, respectively.

Reference numeral 34 is a display correction circuit, which is composed of a minute digit input circuit 36 and an hour digit input circuit 38 for applying counting signals to the minute counter 12 and the hour counter 18, respectively.

The minute digit input circuit 36 outputs the operation signal from the minute correction switch 30 to one input end via an output selection circuit described later and outputs the same as the AND gate 40 which inputs the clock signal ₁ to the other input end. An AND gate 42 for inverting the operation signal via the selection circuit and inputting the inverted signal to one input end and inputting a carry signal from the second counter 10 to the other input end, and output signals of these AND gates 40, 42 The OR gate 44 inputs and outputs a signal to the 1-minute counter 14.

Further, the hour digit input circuit 38 inputs an operation signal from the hour correction switch 28 to one input end via the output selection circuit and inputs the clock signal ₁ to the other input end.
Similarly, an AND gate 48 that inverts the operation signal via the output selection circuit and inputs the inverted signal to one input terminal and the carry signal from the 10-minute counter 16 to the other input terminal, and the output Q of the 10-minute counter 16 AND gate 50 for inputting signals from ₀ and Q ₁ , OR gate 52 for inputting its output signal and the signal from output Q ₂ of 10-minute counter 16, and its output signal for inputting to data input D will be described later. A flip-flop (hereinafter abbreviated as "FF") 54 for inputting a signal R ₁ from a reset circuit to a clock input C, a signal from its output Q and signals from AND gates 46 and 48 are input to the hour counter 18 Or gate 56 applied to
It consists of and.

The AND gate 50, the OR gate 52, and the FF 54 constitute a distribution circuit for advancing the hour counter 18 by one when the 10-minute digit of the time at the time of reset correction is 30 to 50.

Reference numeral 58 denotes a reset circuit, which outputs the hour correction switch 28 and the minute correction switch 3 through an output selection circuit described later.
OR gate 60 for inputting the operation signal from 0, FF 62 for inputting the output signal to the clock input C and inputting the signal from the output to the data input D, the signal from the output Q and the first frequency division Clock signal from unit 6
₃ is input to the data input D and the clock input C, respectively, and further from the output Q, 1-minute counter 14 and 10-minute counter 1
6 and an FF 64 that applies a signal R ₂ to each reset input R of the FF 62.

Reference numeral 66 denotes a reset control circuit, which includes a NOR gate 68 for inputting operation signals from the hour correction switch 28 and the minute correction switch 30, an FF 70 for inputting the signal R ₁ from the reset circuit 58 to the set input S, and an output Q thereof. Signal from the NOR gate 68 and the signal from the NOR gate 68 to the data input D and the clock input C, respectively, and outputs the control signal from the output Q, the signal from the output and the inverter 74
The OR gate 76 which inputs the signal from the NOR gate 68 inverted at, the output signal and the clock signal ₀ are input to the reset input R and the clock input C, respectively, and the signal is output from the output Qn to the reset input R of the FFs 70 and 72. And an n-ary counter 78 for applying.

An output selection circuit 80 inputs AND gates 82 and 84 for inputting an operation signal from the time correction switch 28 to each one input terminal and a control signal and its inverted signal to the other input terminals respectively. It is composed of AND gates 86 and 88 for inputting the operation signal from the correction switch 30 to each one input terminal and for inputting the control signal and its inverted signal to the other input terminals respectively.

Next, the operation of the correction circuit having the above configuration will be described with reference to the time chart shown in FIG.

First, the clock signal output from the second counter 10 is
It is applied to the one-minute counter 14 through the AND gate 42 and the OR gate 44 in the normally open state and counted.

The carry signal output by the 1-minute counter 14 every 10 minutes is applied to the 10-minute counter 16. Also, this 10
The carry signal output from the minute counter 16 every 60 minutes is applied to the hour counter 18 via the normally open AND gate 48 and the OR gate 56, and is counted here.

Now, when the hour correction switch 28 or the minute correction switch 30 is operated, an H level operation signal is generated at the output of the normally open AND gate 84 or 88.

This operation signal is applied to the clock input C of the FF 62 via the OR gate 60, and the FF 62 sets the signal R ₁ from its output Q to the H level in synchronization with its rising edge. When the signal R ₁ becomes H level in this way, the second frequency divider 8 and the second counter 10 are simultaneously reset.

If the 10-minute digit of the time at this time is 30 to 50, an H-level signal is applied to the data input D of the FF 54 due to the states of the outputs Q _{0 to} Q ₂ of the 10-minute counter 16. Therefore, the FF 54 outputs an H level signal from its output Q in synchronization with the rising of the signal R ₁ .

When this signal is input through the OR gate 56, the counter 18 advances the count by one step.

Further, when the signal R ₁ becomes H level, the FF 64 makes the signal from the output Q thereof become H level in synchronization with the clock signal ₃ . Then, by this signal, the 1-minute counter 14 and 1
The 0 minute counter 16 is reset. Also at this time,
The signal R ₂ from the output Q of the FF 64 is also applied to the reset input R of the FF 62 and resets it.
As a result, pulses are sequentially generated at the outputs Q of 62 and 64, and the minute counter 12 is reset after the distribution circuit including the FF 54 is operated.

On the other hand, when a pulse is generated in the signal R ₁ from the FF 62 as described above, the FF 70 which inputs this to the set input S is set, and the output Q thereof outputs a signal of H level.

Here, when the hour correction switch 28 or the minute correction switch 30 is turned off, the operation signal that is output becomes L level, and the output signal of the NOR gate 68 that inputs this becomes H level.

Therefore, the H level signal from the FF 70 is input to the data input D
The FF 72, which is input to, outputs its output Q and H level in synchronization with the rising edge of the signal from the NOR gate 68, respectively. The control signal from the output Q of this FF72 is H
At the level, the AND gates 82 and 86 are opened instead of the AND gates 84 and 88. Also, FF72
OR gate 7 for inputting a signal from an inverter 74 that inverts the signal from the output Q of
The output signal of 6 goes to L level, whereby the n-ary counter 78 is released from reset and starts counting.

When the hour correction switch 28 or the minute correction switch 30 is operated in this state, the operation signals are generated at the outputs of the AND gates 82 and 86, respectively, and the AND gates 46 and 40 are opened. Therefore, the clock signal ₁ is generated at the outputs of the AND gates 46 and 40 and applied to the hour counter 18 and the 1-minute counter 14 via the OR gates 56 and 44, respectively, to fast-forward and correct these counts.

Since the output signal of the NOR gate 68 becomes L level during such correction, the n-ary counter 78 which inverts the signal and inputs it to the reset input R is reset every time the switch is operated.

Here, when both the hour correction switch 28 and the minute correction switch 30 are turned off, the n-ary counter 78 counts without being reset, and after counting for a predetermined time, the output Qn outputs a carry signal of H level. By this signal, the FFs 70 and 72 are reset, the control signal from the output Q of the FF 72 becomes L level, and the AND gates 84 and 88 are opened again instead of the AND gates 82 and 86. When the signal from the output of the FF 72 becomes H level, the n-ary counter 78 is kept in the reset state and its output Qn also becomes L level.

As described above, if the switch is left without operating the switch after the initial operation, the n-adic counter 78 is operating at this time, and after a certain period of time, the FFs 70, 72 are output by the signal from the output Qn. Is reset. Therefore, the subsequent switch operation is the first operation described above, and the minute counter 12 is reset and corrected on the hour.

(Effects of the Invention) According to the present invention, when the switch is operated for the first time, it is possible to set the hour on the hour no matter which switch is operated.
The time can be adjusted easily and reliably.

[Brief description of drawings]

FIG. 1 is a diagram showing the configuration of a correction circuit for a digital timepiece according to an embodiment of the present invention, and FIG. 2 is a time chart of the signals shown in FIG. 2 ... Time signal generating circuit, 12 ... minute counter, 18 ... hour counter, 20 ... display circuit, 28 ... hour correction switch, 30 ... minute correction switch, 34 ... display correction circuit, 58 ... Reset circuit, 66 ... Reset control circuit, 80 ... Output selection circuit.

Claims (1)

[Scope of utility model registration request] 1. A time signal generating circuit for generating a time signal, a minute counter for counting the minute digits of the time by the time signal, and an hour counter for counting the hour digits of the time by a carry signal from the minute counter. , A display circuit for displaying the time counted by the hour counter and the minute counter, a switch group for outputting an operation signal by an external operation, and correcting the counts of the hour counter and the minute counter according to the operation signal, In a correction circuit of a digital timepiece having a display correction circuit for correcting the display of a display circuit, a reset signal is applied to and cleared by the minute counter in response to any operation signal from the switch group. A reset circuit that applies a reset signal to the display correction circuit to advance the count of the hour counter when carrying a carry; A reset control circuit that outputs a control signal that blocks the generation of a reset signal for a certain period of time in response to the stoppage of the operation signal when the output signal is generated, and supplies the operation signal to the display correction circuit when the control signal is generated A correction circuit for a digital timepiece, comprising: an output selection circuit for supplying the operation signal to the reset circuit when the control signal is not generated.