JPS62134096U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the circuit configuration of a digital clock according to an embodiment of the present invention, and FIGS. 2 to 4 are time charts. 2... Oscillator, 4... Frequency dividing circuit, 8... Timing circuit, 14... External switch for correction, 16, 30...
...Counter, 20, 28...Flip-flop,
22, 24...and gate, 26...or gate.

Claims (1)

[Claims for Utility Model Registration] A reference signal generator; a timekeeping circuit that counts the current time using a signal from the reference signal generator; an external correction switch that supplies a single correction signal to the timekeeping circuit; a first counter that counts the signal from the reference signal generator only when the external correction switch is operated; and a first counter that counts the signal from the reference signal generator only when the external correction switch is operated; a switching circuit that supplies a correction fast-forward signal from the reference signal generator to the timekeeping circuit in place of the correction single-shot signal until the end of the correction; Counting direction inversion, comprising a counter, detecting that the signal supplied from the switching circuit to the timekeeping circuit has switched from a fast-forward signal for correction to a single-shot signal for correction, and inverts the counter direction of the up-down counter. From the time when the counting direction of the up-down counter is switched by the counting direction reversing circuit, the signal of the reference signal generator can be counted, and after the external correction switch is no longer operated. A correction device for a digital timepiece, comprising: a second counter that outputs a signal that returns the counting direction reversal circuit to its original state after a certain period of time has elapsed.