JPS6310471U - - Google Patents

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Publication number
JPS6310471U
JPS6310471U JP10413786U JP10413786U JPS6310471U JP S6310471 U JPS6310471 U JP S6310471U JP 10413786 U JP10413786 U JP 10413786U JP 10413786 U JP10413786 U JP 10413786U JP S6310471 U JPS6310471 U JP S6310471U
Authority
JP
Japan
Prior art keywords
circuit
reference clock
measuring
loop
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10413786U
Other languages
Japanese (ja)
Other versions
JPH082623Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986104137U priority Critical patent/JPH082623Y2/en
Publication of JPS6310471U publication Critical patent/JPS6310471U/ja
Application granted granted Critical
Publication of JPH082623Y2 publication Critical patent/JPH082623Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の実施例を示す回路図、第２
図はループ発振をさせるか否かを切り替える手段
の例を示す回路図、第３図は回路が信号に与える
時間遅延量を測定する従来の回路例を示す図であ
る。 １１：第１アンドゲート、１２：第２アンドゲ
ート、１３：基準クロツク、１４，１５：選択信
号、１６：第１オアゲート、１７：第１可変遅延
回路、１８：オアゲート、１９：出力端、２１：
第２オアゲート、２２：第２可変遅延回路、２３
：処理装置、２４，２５：レジスタ、２６：オア
ゲート、２７：第３アンドゲート、２８：第４ア
ンドゲート、２９：スタートパルス、３１：カウ
ンタ、３２：イネイブル信号、３４：第１ループ
回路、３５：第２ループ回路、３６：マルチプレ
クサ、３７：測定モード信号、３８，３９：切り
替える手段、４１：アンドゲート、４２：インバ
ータ、４３：アンドゲート、４４：オアゲート。 Figure 1 is a circuit diagram showing an embodiment of this invention, Figure 2 is a circuit diagram showing an embodiment of this invention.
The figure is a circuit diagram showing an example of means for switching whether or not to cause loop oscillation, and FIG. 3 is a diagram showing an example of a conventional circuit for measuring the amount of time delay given by the circuit to a signal. 11: First AND gate, 12: Second AND gate, 13: Reference clock, 14, 15: Selection signal, 16: First OR gate, 17: First variable delay circuit, 18: OR gate, 19: Output end, 21 :
Second OR gate, 22: Second variable delay circuit, 23
: Processing device, 24, 25: Register, 26: OR gate, 27: Third AND gate, 28: Fourth AND gate, 29: Start pulse, 31: Counter, 32: Enable signal, 34: First loop circuit, 35 : second loop circuit, 36: multiplexer, 37: measurement mode signal, 38, 39: switching means, 41: AND gate, 42: inverter, 43: AND gate, 44: OR gate.

Claims (1)

【実用新案登録請求の範囲】 基準クロツクにて動作する論理回路において、
回路の出力信号を帰還させる手段と、 基準クロツクと帰還信号とを選択する手段と、
ループ発振をさせるか否かを切り替える手段と、
ループの周期を測定する手段とを有し、基準クロ
ツクの経路を経由したループ発振の発振周期を測
定することを可能とした回路の遅延量測定回路。[Claims for Utility Model Registration] In a logic circuit that operates with a reference clock,
means for feeding back the output signal of the circuit; means for selecting the reference clock and the feedback signal;
A means for switching whether or not to cause loop oscillation;
What is claimed is: 1. A delay amount measuring circuit for a circuit which has means for measuring a loop period and is capable of measuring an oscillation period of loop oscillation via a reference clock path.
JP1986104137U 1986-07-07 1986-07-07 Delay amount measurement circuit Expired - Lifetime JPH082623Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986104137U JPH082623Y2 (en) 1986-07-07 1986-07-07 Delay amount measurement circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986104137U JPH082623Y2 (en) 1986-07-07 1986-07-07 Delay amount measurement circuit

Publications (2)

Publication Number Publication Date
JPS6310471U true JPS6310471U (en) 1988-01-23
JPH082623Y2 JPH082623Y2 (en) 1996-01-29

Family

ID=30977354

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986104137U Expired - Lifetime JPH082623Y2 (en) 1986-07-07 1986-07-07 Delay amount measurement circuit

Country Status (1)

Country Link
JP (1) JPH082623Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007138814A1 (en) * 2006-05-26 2007-12-06 Advantest Corporation Testing apparatus and test module

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59154367A (en) * 1983-02-23 1984-09-03 Mitsubishi Electric Corp Measuring device of delay quantity

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59154367A (en) * 1983-02-23 1984-09-03 Mitsubishi Electric Corp Measuring device of delay quantity

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007138814A1 (en) * 2006-05-26 2007-12-06 Advantest Corporation Testing apparatus and test module
JP5100645B2 (en) * 2006-05-26 2012-12-19 株式会社アドバンテスト Test equipment and test modules

Also Published As

Publication number Publication date
JPH082623Y2 (en) 1996-01-29

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