JPH082623Y2 - Delay amount measurement circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial application field" The present invention relates to a delay amount measuring circuit for measuring the signal delay amount of a plurality of variable delay circuits incorporated in a circuit.

"Prior Art" FIG. 3 is a diagram showing an example of a conventional delay amount measuring circuit for measuring a time delay amount given to a signal by a variable delay circuit. First
A common reference clock 13 is supplied to the AND gate 11 and the second AND gate 12, and its first and second AND gates are supplied.
The selection signals 14 or 15 are supplied to the other input terminals of 11, 12 respectively. Under test mode, select signal 14 or
The reference clock 13 is output from the first AND gate 11 or the second AND gate 12 selected by 15. The reference clock 13 output from the first AND gate 11 is supplied to the first variable delay circuit 17 via the first OR gate 16, and receives the _first time delay amount D ₁ set in the first variable delay circuit 17. Is output. The reference clock 13A that has received the time delay amount D ₁ is output from the output terminal 19 via the OR gate 18. Further, the second AND gate 12 is selected, and the reference clock 13 that has passed through the second AND gate 12 passes through the second OR gate 21 to the second
It is supplied to the variable delay circuit 22 and receives and outputs the _second time delay amount D ₂ set in the second variable delay circuit 22. The reference clock 13B that has received the time delay amount D ₂ is output from the output terminal 19 via the OR gate 18.

This circuit is incorporated in, for example, an IC test apparatus, and is used when it is desired to change the timing of a signal given to an integrated circuit under test. For example, the processing device 23 of the IC test device outputs data defining the time delay amounts D ₁ and D ₂ of the first and second variable delay circuits 17 and 22 to the registers 24 and 25, and the register 24 and 25
The data values of 25 determine the time delay amounts D ₁ and D ₂ given to the reference clock by the first and second variable delay circuits 17 and 22.

The IC test apparatus may need to know the actual value of this time delay amount in order to set a delicate timing. At such time, the first and second variable delay circuits 17, 22
To measure the time delay amounts D ₁ and D ₂ given to the reference clock 13 by the OR gate 26 between the output terminal of the OR gate 18 and the other input terminals of the first OR gate 16 and the second OR gate 21, respectively. 3rd AND gate 27 or OR gate 26 and 4th
AND gate 28 is interposed. That is, the output terminal of the OR gate 18 is connected to the input terminal of the OR gate 26, and the output of the OR gate 26 is the third AND gate 27 and the fourth AND gate.
28, and the outputs of the third AND gate 27 and the fourth AND gate 28 are supplied to the other input terminal of the first OR gate 16 or the second OR gate 21, respectively.

A start pulse 29 is applied to the other input terminal of the OR gate 26 and supplied to the first and second variable delay circuits 17 and 22 via the OR gate 26 and the third or fourth AND gate 27 or 28. The output of the OR gate 26 is also supplied to the counter 31.

In this configuration, in order to measure the time delay amount D ₁ given to the reference clock 13 by the first variable delay circuit 17 under the measurement mode, the enable signal 32A is supplied to the other input terminal of the third AND gate 27, The third AND gate 27 is controlled to be in the gate open state, and the fourth AND gate 28 is controlled to be in the gate closed state, and the OR gate 26, the third AND gate 27, the first OR gate 16, the first variable delay circuit 17, and the OR gate 18 are controlled. Then, the first loop circuit 34 of the OR gate 26 is formed. A start pulse 29 having an extremely narrow pulse width is supplied to the first loop circuit 34 from the other input terminal of the OR gate 26. The start pulse 29 circulates in the loop circuit 34 including the first variable delay circuit 17, and is supplied as a count clock to the counter 31 for counting every time it circulates once. The time delay amount D ₁ of the first loop circuit 34 can be known by reading the count value of the counter 31 per unit time.

When the first AND gate 11 is closed and the second AND gate 12 is controlled to be open, and the enable signal 32B is supplied to the other input terminal of the fourth AND gate 28, the OR gate 26
AND gate 28, second OR gate 21, second variable delay circuit 2
2, OR gate 18 and OR gate 26 second loop circuit 35
Is configured. The amount of time delay D of this second loop circuit 35
₂ can be measured similarly to the first loop circuit 34.

“Problems to be solved by the device” In such a conventional measurement method, the signal path when measuring the delay time is different from the signal path when the reference clock 13 actually passes, and the accurate time delay is The quantity cannot be measured. That is, in the measurement mode, the signal path when the time delay amount D ₁ of the first variable delay circuit 17 is measured is through the third AND gate 27 and the first OR gate 16, that is, the start pulse 29 is output by the first loop circuit. While being supplied to the first delay circuit 17, the fourth AND gate 28 and the second OR gate 21 are used when measuring the time delay amount D ₂ of the second variable delay circuit 22.
Via the second loop circuit, that is, the second variable delay circuit
Supplied to 22. Further, in the test mode, the path through which the reference clock 13 passes through the first variable delay circuit 17 is supplied to the first variable delay circuit 17 through the first AND gate 11 and the first OR gate 16, and passes through the second variable delay circuit 22. Is supplied through the second AND gate 12 and the second OR gate 21. Therefore,
At the time of measuring the time delay amount in the measurement mode and at the time of normal circuit operation in the test mode, the time delay amount received by the reference clock 13 is the first AND gate 11 and the third AND gate 27 of the first loop circuit, Since the four gates of the second AND gate 12 and the fourth AND gate 28 of the second loop circuit are involved, they are affected by the difference in the time delay amount of these gates.

"Means for solving the problem" The outputs of a plurality of AND gates to which a common reference clock is given are supplied to the variable delay circuits capable of setting the delay amount from the outside respectively, and the outputs of these variable delay circuits are supplied. The signals are output through a common OR gate, and a selection signal is supplied to each of a plurality of AND gates. One of these selection signals is used as an H signal, and one of these AND gates is selectively opened to cause a different delay with respect to the reference clock. In a variable delay circuit capable of selectively obtaining a given clock, a first switching means for switching between a reference clock and an output clock of an OR gate and supplying it to a plurality of AND gates, and a means provided for each AND gate, By switching the selection signal to be supplied to the gate and the enable signal for each AND gate, And a second switching unit for supplying the output clock of the OR gate to the AND gate, and a loop oscillation frequency measuring unit configured to measure the loop oscillation frequency. The first switching unit supplies the reference clock. The second switching means supplies the selection signal to the AND gate while supplying the AND gate, and the second switching means supplies the enable signal to the AND gate while supplying the output of the OR gate to the AND gate. Only one enable signal is selected as the H signal. By measuring each of the loop oscillation frequencies, it is possible to accurately measure the time delay amount of the plurality of signal paths through which the reference clock passes.

[Embodiment] FIG. 1 is a circuit diagram showing an embodiment of the present invention. Third
The parts corresponding to those in the figure will be described with the same reference numerals.

In the present invention, the outputs of the variable delay circuits 17 and 22, that is, the signal output of the OR gate 18 are supplied to the input end 36A of the multiplexer 36 via the OR gate 26, and the reference clock 13 is applied to the other input end 36B of the multiplexer 36. Is supplied. The multiplexer 36 is provided with first switching means for selectively supplying the fed back output signal of the OR gate 26 and the reference clock 13 to the input terminal of the AND gate. That is, the measurement mode signal 37 is supplied to the selection input terminal 36C of the multiplexer 36. For example, measurement mode signal
When 37 is the L signal, it is in the test mode and the reference clock
13 is output from the multiplexer 36 and supplied to the first and second AND gates 11 and 12, and when the measurement mode signal is the H signal, the measurement mode is entered, and the multiplexer 36 returns the feedback signal of the logic circuit to the first and second AND gates. It is supplied to one input terminal of the gates 11 and 12.

In FIG. 1, the first loop circuit 34 is a multiplexer 3
6, first AND gate 11, first variable delay circuit 17, OR gate
18, the OR gate 26 and the multiplexer 36, and the second loop circuit 35 is formed by the multiplexer 36, the second AND gate 12, the second variable delay circuit 22, the OR gate 18, the OR gate 26 and the multiplexer 36.

At the other input terminals of the first and second AND gates 11 and 12,
A second switching circuit for interlocking with the first switching circuit to determine whether or not the first and second loop circuits 34 and 35 are caused to perform the loop oscillation.
The selection signal and the enable signal are supplied by the switching means 38 and 39, respectively.

FIG. 2 is a circuit diagram showing an example of the second switching means 38, 39 for switching the signal as to whether or not to cause the loop oscillation. This circuit example is an example configured so that it is not necessary to change the control program of the processing device 23 of the conventional IC test device. The measurement mode signal 37 is supplied to one AND gate 41 and the other AND gate 43 via the inverter 42, the enable signal 32A or 32B is supplied to one AND gate 41, and the selection signal 14 or 15 is supplied. Is supplied to the other AND gate 43. If both measurement mode signal 37 and enable signal 32A are H signals, AND gate 4
The loop oscillation enable selection signal H is supplied from 1 to the input terminal 11A of the first AND gate 11 via the OR gate 44, and the first loop circuit 34 is controlled to a state in which loop oscillation is possible. At this time, the enable signal 32B is simultaneously changed to the L signal, and the second signal
Loop oscillation prohibition signal L is applied to the input terminal 12A of the AND gate 12.
Is supplied. In this state, the start pulse 29 is supplied to the input end of the OR gate 26. Multiplexer 36
Is supplied with an H measurement mode signal 37, and the start pulse 29 goes around the first loop circuit 34 passing through the multiplexer 36, the first AND gate 11 and the first variable delay circuit 17. The start pulse 29 is supplied to the counter 31 as a counting clock and counted every time the loop circulates once.
Therefore, the first AND gate 1 including the multiplexer 36
1, first variable delay circuit 17, OR gate 18 and OR gate 26
It is possible to measure the time delay amount D ₁ of the signal related to. On the other hand, when the second loop circuit 35 is oscillated, the time delay amount D ₂ of the signal involving the second AND gate 12, the second variable delay circuit 22, the OR gate 18, and the OR gate 26 including the multiplexer 36 is measured. can do.

In this embodiment, the first and second loop circuits 34 and 35 include the multiplexer 36, the OR gate 18 and the OR gate 26 as common circuit elements, and therefore, the delay time D _{1 of} these two loop circuits 34 and 35 is included. And D ₂ are due only to the difference between the first AND gate 11, the first variable delay circuit 17 and the AND gate 12, the second variable delay circuit 22.

Further, according to this circuit configuration, even when the test mode is set and the reference clock 13 is supplied, the difference between the two paths through which the reference clock passes is that the first AND gate 11, the first variable delay circuit 17 and the AND gate are different. 12, the second variable delay circuit 22 and the difference between the two paths through which the start clock 29 passes in the measurement mode.

That is, the first and second variable delay circuits measured in the measurement mode
The time delay amount of 17,22 is 1st and 2nd AND gate 1 respectively
Although it cannot be said to be exact due to the influence of the gate delay of 1,12, it exactly matches the difference between the time delay amounts D ₁ and D ₂ of the _two paths in the test mode. Therefore, according to this invention, it is possible to set the difference in the amount of time delay given to the signal by the two paths through which the reference clock 13 passes or the phase difference given to the signal to a desired amount.

Although it has been described above that the time delay amount of the branch path that is branched into two and includes different variable delay circuits is measured, the present invention does not relate only to the path branched into two. The amount of time delay of the path branched into three or more can be measured in the same manner.

[Effect of the device] Since the clock path on the logic circuit that measures the delay amount of the multiple variable delay circuits in the measurement mode and the path on the multiple logic circuits through which the reference clock passes in the test mode are the same. , It has become possible to accurately measure the amount of time delay of signals on a plurality of paths through which a reference clock passes. As a result, when it is used in, for example, a pattern generator of an IC test apparatus, the accuracy of setting signal timing can be improved, and therefore the accuracy of testing an integrated circuit can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of means for switching whether or not to perform loop oscillation, and FIG. 3 is a circuit for measuring a time delay amount given to a signal by the circuit. It is a figure which shows the conventional circuit example. 11: First AND gate, 12: Second AND gate, 13: Reference clock, 14, 15: Selection signal, 16: First OR gate, 17: First variable delay circuit, 18: OR gate, 19: Output terminal, 21 : Second
OR gate, 22: second variable delay circuit, 23: processing device, 24, 2
5: Register, 26: OR gate, 27: Third AND gate, 2
8: Fourth AND gate, 29: Start pulse, 31: Counter, 32: Enable signal, 34: First loop circuit, 35: Second
Loop circuit, 36: first switching means (multiplexer), 37: measurement mode signal, 38, 39: second switching means 4
1: AND gate, 42: Inverter, 43: AND gate, 4
4: OR gate.

Claims (1)

[Scope of utility model registration request] 1. Outputs of a plurality of AND gates to which a reference clock is commonly given are supplied to respective variable delay circuits capable of setting a delay amount, and outputs of these variable delay circuits are passed through a common OR gate. A clock that is output and is supplied with a selection signal to each of the plurality of AND gates, and one of the selection signals is used as an H signal to selectively open one of the AND gates to give a different delay to the reference clock. In the variable delay circuit adapted to selectively obtain, the first switching means for switching between the reference clock and the output clock of the OR gate and supplying the plurality of AND gates, and each of the AND gates. By switching the selection signal to be supplied to the gate and the enable signal for each AND gate, And a second switching means for supplying to the AND gate, and a means for measuring a loop oscillation frequency configured in a state where the first switching means supplies the output clock of the OR gate to the AND gate. The second switching means supplies the selection signal to the AND gates while the first switching means supplies the reference clock to the respective AND gates, and only one of the enable signals is an H signal. A delay amount measuring circuit selectively made to.